EECS 270: Lab 6

Complex State Machines: Traffic light controller

See the lab schedule for due dates.
Value: 125 points + up to 5 points of extra credit.

  1. Overview
  2. It is often the case that a real world problem requires a fair bit of complexity and multiple devices working in tandem. In this lab you will design a state machine which controls a set of traffic lights.

    Your state machine will also interact with another device: a 4-bit binary counter. Your state machine will control that counter and use it as an input. This type of interaction between a state machine and another device is fairly common---and in this case greatly reduces the number of states needed.

  3. Preparation
  4. It would be helpful to review the Verilog sequential logic tutorial on the main lab page.

  5. Design Specification
  6. This lab is to be done purely in Verilog.

    In this lab, there are 5 inputs (the traffic sensors), and 5 outputs (the traffic lights associated with each sensor) and a reset. The sensor names are:

    The sensors are all either on (indicating a car is present in that lane) or off (indicating no car is present).

    The traffic lights associated with each direction have the same name, but end in a "TL". So WSTL is the West-bound straight traffic light. Each light can be Green, Yellow or Red.


    Figure 1: The intersection

    The system clock is assumed to have a period of 1 second.

    Your traffic light controller is to follow the following rules. These rules are NOT a complete specification. That is, there is some ambiguity in what to do in certain situations. You need to pick some reasonable behavior for those situations.

    1. Two lanes of traffic are considered to "conflict" if having both of them going at the same time could cause a collision (that is if their paths cross). For example, having the both North-bound left lane and the west-bound left lane having a Green or Yellow light at the same time could cause a collision, so those lanes are considered to "conflict".
    2. No two lanes in conflict should have "Green" or "Yellow" at the same time.
    3. When a light is to change from Green to Red, it should be Yellow for exactly one second in between the Green and Red.
    4. There should be no "starvation". That is, if a given sensor is on, its lane should get a Green light at some point, no matter the state of the other sensors.
    5. When sensors for two conflicting lanes are on, no one direction should be Green for more than 10 seconds.
    6. When only one sensor is on, that light must become and stay Green until some sensor input changes. It still needs to follow the above rules!
    7. If either North-bound lane sensor is on, the duration of its Green must be at least 7 seconds, no matter the state of the other sensors. (If it goes off, the Green can be taken away immediately).
    8. No Green should be less than 3 seconds in duration.
    9. When no sensor is on, the default configuration should be having both North-bound lights Green. All other lights should be Red.
    10. The traffic lights should behave in a way that you think would best move traffic through the intersection given the above rules. You are to assume the sensors are prefect and will always detect a car if one is there.
    11. In general it is best to avoid having Red lights. So it should never be the case that a given light could be Green but isn't.
    12. The controller should have a reset. When reset is high the system should go to and stay in the default state (defined above).

    The counter
    All timing-related issues greater than 1 second are to be handled by a 4-bit saturating counter. You may use >, < and == to compare to the current value of the counter. The only control you have over the counter is a reset line. The code you are to use for the counter is on the main lab page.

    Mapping inputs and outputs

    The counter should be displayed as an unsigned number on the left-most hex displays. You may do this in decimal (so 2 hex displays) or hex (1 hex display). You may copy a hex decoder from the web or other source (not a fellow student) if you wish. If you do that, you must site where you got it from in your post-lab!

    Finally, be careful to design your state machine in a way similar to the one we provided as an example in the sequential logic handout. If nothing else, it will make the post-lab a lot easier. You are required to have separate always blocks for the next-state logic and the output logic.

  7. Design Notes and Hints
  8. Deliverables
  9. Pre-Lab (40 Points)
    Draw a state diagram which implements your controller. The logic on the transitions may be fairly complex, so feel free to simply label the transitions and put the logic equation elsewhere on the page. As in the previous lab, ignore reset in this diagram. Use the naming conventions used above. You should expect to have things like "Counter<3" and the like as conditions on your state machine. Also think about when you want to reset the counter (this should be an output of your state machine).

    In-lab (55 points)
    Demonstrate your lab to your lab instructor.

    Post-Lab (30 Points + 5 possible extra credit points)

    1. Consider segment 3 of the hex display for NLTL. Write the minimal sum-of-products which shows how the state controls that segment. Show the K-map or truth table. The point here is to remind you what your tools are doing for you. (10 points)

    2. If you copied your binary to 7-segment hex display code from the web, tell us where you got it from. (0 points, but required if you copied it.)

    3. The combinational state machine components (next state and output) can be expressed as truth tables.
      1. List the inputs and outputs for each combinational state machine component. (5 points).
      2. How many rows and columns does each table have? Only count the output columns. (5 points).
    4. The states of the FSM are kept in the memory of the sequential FSM component. (FSM stands for Finite State Machine.)
      1. How many D flip-flops are required to hold all your states? (3 points).
      2. Do you have unused states? If so, how many? (4 points).
      3. If you used a one-hot encoding, how many D flip-flops would you need? (3 points).

    5. Extra credit: Get a real 1 second clock sent as your clock input. (Hint: see lab 7...) (5 points).