Design Specification
This lab is to be done purely in Verilog.
In this lab, there are 5 inputs (the traffic sensors), and 5 outputs (the
traffic lights associated with each sensor) and a
reset. The sensor names are:
- WS -- West-bound straight
- WL -- West-bound left turn
- NR -- North-bound right turn
- NL -- North-bound left turn
- E -- East-bound (both right and straight)
The sensors are all either on (indicating a car is present in that lane) or
off (indicating no car is present).
The traffic lights associated with each direction have the same name, but end
in a "TL". So WSTL is the West-bound straight
traffic light. Each light can be Green, Yellow or Red.

Figure 1: The intersection
The system clock is assumed to have a period of 1 second.
Your traffic light controller is to follow the following rules. These rules
are NOT a complete specification. That is, there is some ambiguity in what
to do in certain situations. You need to pick some reasonable behavior for
those situations.
- Two lanes of traffic are considered to "conflict" if having both of them
going at the same time could cause a collision (that is if their paths
cross). For example, having the both North-bound left lane and the
west-bound left lane having a Green or Yellow light at the same time could
cause a collision, so those lanes are considered to "conflict".
- No two lanes in conflict should have "Green" or "Yellow" at the same
time.
- When a light is to change from Green to Red, it should be
Yellow for exactly one second in between the Green and Red.
- There should be no "starvation". That is, if a given sensor is on, its
lane should get a Green light at some point, no matter the state of the
other sensors.
- When sensors for two conflicting lanes are on, no one direction should
be Green for more than 10 seconds.
- When only one sensor is on, that light must become and stay Green until some sensor
input changes. It still needs to follow the above rules!
- If either North-bound lane sensor is on, the duration of its Green
must be at least 7 seconds, no matter the state of the other sensors.
(If it goes off, the Green can be taken away immediately).
- No Green should be less than 3 seconds in duration.
- When no sensor is on, the default configuration should be having both
North-bound lights Green. All other
lights should be Red.
- The traffic lights should behave in a way that you think would best move
traffic through the intersection given the above rules. You are to assume the
sensors are prefect and will always detect a car if one is there.
- In general it is best to avoid having Red lights. So it should never
be the case that a given light could be Green but isn't.
- The controller should have a reset. When reset is high the system
should go to and stay in the default state (defined above).
The counter
All timing-related issues greater than 1 second are to be handled by a 4-bit
saturating counter. You may use >, < and == to compare to the current
value of the counter. The only control you have over the counter is a reset
line. The code you are to use for the counter is on the main lab page.
Mapping inputs and outputs
- The clock is to be the left-most push-button.
- The sensors E, WS, WL, NR, and NL should be dipswitches 0 to 4 in that
order.
- The traffic light status should be displayed on the hex displays 0 to 4
in the same order as their respective sensors.
- When Red, the display should be "r".
- When Green, the display should be "g".
- When Yellow, the display should be "E"
The counter should be displayed as an unsigned number on the left-most hex
displays. You may do this in decimal (so 2 hex displays) or hex (1 hex
display). You may copy a hex decoder from the web or other source (not a
fellow student) if you wish. If you do that, you must site where you
got it from in your post-lab!
Finally, be careful to design your state machine in a way similar to the one
we provided as an example in the sequential logic handout. If nothing else,
it will make the post-lab a lot easier. You are required to have separate
always blocks for the next-state logic and the output logic.