| IN0 | IN1 | IN2 | OUT |
b) Draw a circuit to implement the three-input NOR gate using three P-type transistors and three N-type transistors. The diagram should be similar to Figure 3.5 (a).
a) A two-input AND and a two-input OR are both examples of two-input logic functions. How many different two-input logic functions are possible? (For inputs A and B, assume that A OP B is NOT the same function as B OP A).
b) Draw a logical circuit that implements the logic function described
by the following truth table, using only gates from the set {AND,
OR, NOT}. Use the algorithm described in the proof of logical
completeness for the set of gates {AND, OR, NOT}.
| A | B | C | OUT |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
c) Draw another circuit to implement the same function using only gates from the set {NOR, NOT}.
a) How many outputs will a six-input decoder have?
b) Draw a gate-level diagram of a circuit that implements a three-input decoder using only gates from the set {AND, OR, NOT}. Assume that AND and OR gates have as many inputs as are needed for this circuit.
c) If a multiplexer selects among 27 different input lines, how many
select lines must it have?
a) Create a truth table for the following transistor-level gate design for the NEWOP gate shown below.
b) Show how the NEWOP function could be implemented from gates in the set {AND, OR, NOT} if the NEWOP gate were not available.
c) Show that the set of gates {NEWOP, NOT} is logically
complete.
Fill in the truth table for the output value Z shown in the following logic circuit. (Hint: label intermediate points and show their values in the truth table also).
a) How many D-latches would be needed to construct a memory unit with 2^16 uniquely addressable locations in memory and a 24-bit word at each location?
b) What is the address space of the memory described in part a?