HW # 3 Solution

1.

  1. 212 = 4096, so 12 bits are required for an address.

  2. If this memory is divided into 32 pages then each page will contain 4096/32 = 128 addresses.
  3. 5 bits are required to represent each page (25 = 32).
  4. 7 bits are required to represent a specific address within the page (27 = 128).
  5. Address of first word on 4th page is 00011 0000000 = x180
  6. Address of last word on 4th page is 00011 1111111 = x1FF
2.
  1. 2 times (once to fetch the instruction and once to get the new value from memory)
  2. 2 times (once during FETCH cycle, and once to get the new value)
  3. 1 time (once to fetch instruction)
3.
256 service routines are allowed in LC-2 ISA. The TRAP instruction’s opcode is 1111 (i.e. bits (15:12) are all 1), next four bits must be zero (MBZ) and last eight bits are trapvector which determines routines. So there are 28 = 256 trap routines possible.
4.
  1. Instructions at addresses x3006, x3007 and x3008 set condition codes. BR instruction doesn’t set condition codes
  2. Location1 is xFFF0, Location2 is x4000, value at x3000 is x56E0, value at x4000 is x0010
  3. InstrZ will be executed since the result of last operation that changes the condition codes was positive.
5.
  1. Any instruction which sets the condition code without changing the contents of registers. For example ADD R1, R1, #0 or AND R1, R1, R1 (Note: BR doesn’t set condition codes)
  2. There are only two conditions for overflow:
  3.          ; It is assumed that the registers are already loaded
             ADD R3, R2, R1
             BRzn NegTest1
    
             ADD R1, R1, #0    ; result is positive so check for negative operands
             BRzp DONE
             ADD R2, R2, #0    ; R1 is negative so check R2
             BRzp DONE
             BR  OVERFLOW      ; R1 and R2 are negative, but R3 is positive
    
    NegTest1 ADD R1, R1, #0    ; result is negative so check for positive operands
             BRnz DONE
             ADD R2, R2, #0    ; R1 is positive so check R2
             BRnz DONE
             BR  OVERFLOW
    Note: This is just one of the several possible solutions and one of the simpler ones in terms of algorithm. There are other solutions like negating R2 and R1 and adding both to R3 and see if result is 0, etc.
6.
  1. Two LC-2 instructions are needed:
  2.          LDR R2, R1, #0   ; R2 = mem[R1+0]
             STR R2, R0, #0   ; mem[R0+0] = R2 => mem[R0] = mem[R1]
  3. The MOVE instruction wouldn't need a third general-purpose register to transfer the contents of one memory location to another:
  4.          MAR ß SR
             MDR ß mem[MAR]
             MAR ß DR
             mem[MAR] ß MDR