EECS 370 – Exam 1 – 5 Oct 2001

 

Instructors: 

Scott Mahlke or Gary Tyson

Name:

Key,  The

 

 

UID:

 

Honor Code:   I have neither given nor received aid on this exam.

 

uniqname:

 

 

Signature:

 

 

The correct answers at underlined with explanation.

 

 

 

 

 

1. Extrapolating from Moore's law (first lecture) continues to hold, how long will it be before the number of transistors used in current microprocessors is quadrupled?

a.       9 months

b.      18 months

c.       24 months

d.      30 months

e.      36 months   (lecture 1, slide 27)

 

2. In your assembler for programming assignment 1,  .fill is a(n):

a.       instruction

b.      pseudo instruction

c.       assembler directive (lecture 6, slide 4)

d.      linker operation

e.       translation label

 

3. What is the next instruction executed in the following LC2K1 code sequence  assuming that the beq is taken?

nand   0   3   4

beq    4   5   -1

add    2   3   7

lw     3   6   -234

a.       nand

b.      beq   (project 1 writeup: PC+1-1)

c.       add

d.      lw

e.       illegal offset field in beq

 

4. Which of the following events would not cause an exception on the MIPS processor?

a.       Divide by zero

b.      Undefined instruction

c.       Parity error

d.      Illegal memory reference

e.      Invalid register specifier (lecture 12, slides 10 and 11)

5. The design of the register file for the LC2K1 (8 registers, 32-bits each) can use two MUXes to route the data for regA and regB onto the output buses. Alternatively, it can use tri-state drivers; how many tri-state drivers are required (minimum) to replace the two MUXes? (Pick the closest number below).

a.       8

b.      16

c.       64

d.      256

e.      512  (2 MUXes ´ 8 inputs/MUX ´ 32 signals/input ´ 1 driver/signal)

 

6. In the following MIPS code segment, if $3 is caller-saved, at which locations should it be saved/restored?

 

              // start of function foo()

              sub $sp, $sp, 32      // $sp = $sp - 32

            W:

              ...

              add $3, $4, $5        // $3 = $4 + $5

            X:

              jal bar               // call bar (order beer)

            Y:

              lw $7, 8($3)          // $7 = MEM($3+8)

              ...

            Z:

              add $sp, $sp, 32      // $sp = $sp + 32

              jr $31                // return from foo()

 

a.       save at W; restore at Z

b.      save at X; restore at Y (lecture 5, slide 10)

c.       save at W; restore at Y

d.      save at X, restore at Z

e.       $3 does not require saving or restoring

 

7. For the single cycle datapath used in class (and shown in Figure 1), which of the following control ROM entries will not correctly execute the specified instruction?

 

a.       NAND:            1 1 1 1 1 0 1

b.      LW:                 0 0 1 0 0 1 0

c.       SW:                 1 0 0 0 0 1 1

d.      ADD:               1 1 1 1 0 0 0

e.      BEQ:               0 1 1 1 1 0 0  (lecture 9, slide 10)

 

8. What are the values on lines labeled K, L and M in the Carry Look-ahead Adder example given in Figure 2 (with the given inputs)?

a.       K = 0;  L = 0;  M = 0

b.      K = 0;  L = 1;  M = 0

c.       K = 0;  L = 0;  M = 1

d.      K = 1;  L = 1;  M = 0 (lecture 10, slides 7-9)

e.       K = 1;  L = 1;  M = 1

 

9. What is the result of adding the following IEEE 732 floating-point numbers?

1   10000011   01101000000000000000000

0   01111111   11000000000000000000000

 

a.       1   10000010   11010010000000000000000

b.      1   10000011   01001100000000000000000 (Course Text, pg 284)

c.       0   01111111   01101110000000000000000

d.      0   10000010   11010010000000000000000

e.       1   10000011   10101000000000000000000

 

10. If we modified the vending machine discussed in class to accept nickels and dimes in addition to quarters and kept the price of a drink at $0.75, what is the minimum size (measured in edge-triggered D flip-flops) required for the new state machine?

a.       2

b.      3

c.       4 (16 States: 0,5,10,15,20,25,30,35,40,45,50,55,60,65,70,75)

d.      5

e.       6

 

 

11. Given the timing diagrams for the Clock/Gate (C/G) and Data inputs to an Edge-triggered D Flip-Flop, which timing signal most closely approximates the Q output?

 

     b. is the correct answer

 

 

 

 

 

 

 

 

 

 

 


   

 

 

 

 

 

 

 

 

12. Given the initial values in memory locations 100-103 (below left), which of the following MIPS code fragments will result in the new values for location 100-103 seen on the right?

            Initial: Mem[100]   0x00          New: Mem[100]  0x85

                        Mem[101]   0xFF                   Mem[101]  0x58

                        Mem[102]   0x85                    Mem[102]  0x85

                        Mem[103]   0x58                    Mem[103]  0xFF

 

a.       lbu       $4, 100($0)

lh         $5, 102($0)

sh        $5, 100($4)

sb        $4, 103($0)

 

b.      lb         $4, 101($0)

lhu       $5, 102($0)

sh        $5, 101($4)

sb        $4, 103 ($0)

 

c.       lh         $4, 100($0)

lh         $5, 102($0)

sb        $4, 103($0)

sh        $5, 103($4)

 

d.      lh         $4, 102($0)

lb         $5, 103($0)

sh        $5, 100($4)

sb        $4, 103($0)

 

e.       none of the above

 

 

13. In the LC2k1 multi-cycle datapath (See Figure 3), suppose you wanted to extend the functionality to support a new opcode, madd, which adds the contents of regB to the value at the memory location specified by the contents of regA, storing the result into the register specified by destReg (i.e., destReg = MEM[regA] + regB). Which of the following modifications is not required to allow this instruction to be executed in 6 cycles?

 

a.       add input to MUX4 from  Mdata register

b.      add constant input 0 to MUX5

c.       add input to MUX4 from Rdata2 bus (“ya just don’t need it”)

d.      add  an additional control signal to MUX4

e.       This instruction can’t be executed in 6 cycles with the modifications specified above.

 

14. LC2K1 does not support subtraction. What is the minimum number of LC2K1 instructions required to subtract the contents of one register value from another register? You may assume that any other registers have any constant values that you may need to support subtraction.

a.      3  (NAND(w/self), ADD(+1), ADD)

b.      4

c.       5

d.      more than 5

e.       Can’t be done with any number of LC2k1 instructions

 

 

15. Suppose we wish to execute 100 instructions consisting of 25% loads, 25% stores, 25% branches, and 25% adds with the following propagation delays: 

 

1. memory access: 4 ns

2. register read or write: 1 ns

3. ALU operations: 2 ns

 

In the multi-cycle datapath with a 3-cycle taken branch (as discussed in lecture), a cycle time of 4ns would have to be used, since the maximum propagation delay is a memory access at 4ns. If we modify the design to devote 2 cycles to each memory access, we can reduce the clock cycle time to 2ns.  Given a 2ns clock and a 2-cycle memory access, what is the expected execution time for these 100 instructions?

 

a.       700 ns

b.      800 ns

c.       900 ns

d.      1000 ns

e.      1100 ns    ( 25 ´ (7+6+4+5) ´ 2ns  =  1100 ns)