EECS 370 – Exam 2 – 26 Oct 2001

Instructors:

Scott Mahlke or Gary Tyson

Name:

  
   

UID:

  

Honor Code: I have neither given nor received aid on this exam.

uniqname:

  

Signature:

  

There are 15 multiple-choice questions, each of equal value. Each question has one correct answer. You should mark your answers on the optical grade forms provided. This is a closed book, closed notes examination. You may use a calculator for arithmetic (but not note storage, etc.). Don’t forget to copy your answers so you can compare to the key that will be posted on the website after the exam.

 

 

1. The Pentium Pro and Pentium 4 processors can best be described as:

    1. RISC architecture, RISC implementation
    2. RISC architecture, CISC implementation
    3. CISC architecture, RISC implementation **
    4. CISC architecture, CISC implementation
    5. None of the above

2. In the pipeline design for the LC2k1 described in lecture, which value is not needed in the Ex/MEM pipeline register?
    1. PC+1+offset
    2. aluResult
    3. contents of regA (valA) **
    4. contents of regB (valB)
    5. C and D are not needed

3. In which of the following ways was the multi-cycle LC2K1 datapath modified to obtain the pipelined LC2K1 datapath discussed in lecture?
    1. Introduce adder(s)
    2. Introduce pipeline registers
    3. Introduce general purpose registers
    4. Split instruction and data memory
      1. I, IV
      2. II, IV
      3. III, IV
      4. I, II, IV **
      5. Something other than A,B,C or D

4. Among the following pipelines, whose performance suffers the most from poor branch prediction?
    1. 25 stages, branch resolved at stage 10
    2. 21 stages, branch resolved at stage 12
    3. 15 stages, branch resolved at stage 10
    4. 17 stages, branch resolved at stage 13 **
    5. 5 stages, branch resolved at stage 5

5. Assume clock rate = 200MHz and three instructions with the following multi-cycle execution times:

lw 8 cycles

add 3 cycles

beq 4 cycles

If an application is run on this processor which executes 4200 instructions with the following distribution of opcodes: 20% lw, 50% add, 30% beq.

What is the CPI rounded to the nearest integer (i.e. 1.5 rounds up to 2, 1.49 rounds down to 1)?
    1. 3
    2. 4 **
    3. 5
    4. 6
    5. 7

6. What is the maximum number of active stack frames for the function shown below when making the initial call ( combination(8, 4) )? Note the first frame is created by combination(8,4) itself.

int combination(int n, int r) {

if (r==0 || n==r) {

return(1);

} else {

return(combination(n-1,r) + combination(n-1,r-1));

}

}
    1. 4
    2. 8 **
    3. 12
    4. 24
    5. 256

7. What is wrong with the following definition of a state for Project 2?

beq1: printState(&state, "beq1");

state.pc++;

bus = state.reg[(state.instrReg >> 16) & 0x7];

state.aluResult = state.aluOperand - bus;

if (state.aluResult == 0)

goto beq2;

else

goto fetch1;
    1. This is correct
    2. Can not increment pc
    3. Can not both write to then read from the bus in same cycle
    4. Can not write to then read from the aluResult in the same cycle **
    5. Can not read regB and do ALU operation in the same cycle

 

 

 

 

8. Suppose program A running multi-cycle processor X achieves a CPI of 4.8. In program A, the only thing you know is that 20% of the instructions are branches. Suppose we a change to the processor implementation that reduces the execution time of taken branches from 4 to 3 cycles. What is the best achievable CPI for program A with this change?
    1. 4.8
    2. 4.7
    3. 4.6 **
    4. 4.5
    5. Can not determine with the information provided

9. For the following code executed on the 5-stage pipeline used in lecture, what value is written to the ALU result in the EX/Mem pipeline register at the end of time = 6? (Assume that the first add is written to the IF/ID pipeline register at the end of time = 1, and each register has the value 5 at the start of the code).

add 1 2 3

sw 4 5 15

add 1 4 2

lw 6 6 20

nand 3 4 5
    1. 10
    2. 15
    3. 20
    4. 25 **
    5. 30

10. What modification must be made to the pipeline datapath discussed in lecture to support the LC2K1 JALR instruction?

    1. Include PC in pipeline registers IF/ID and ID/Ex
    2. Route valA in pipeline register ID/Ex to MUX input for PC
    3. Compare regA specifier with regB specifier and route result to control MUX for PC
    4. A and B
    5. B and C **

 

11. In the LC2K1 pipeline implementation with data forwarding support, which pipeline register(s) contain value(s) that will be forwarded at time=5 for the following LC2K1 code? (note: the add instruction is written to the IF/ID pipeline register at time=1)

add 1 2 3

nand 3 2 2

beq 2 3 25

halt

    1. Mem/WB: Memdata
    2. Mem/WB: Alu Result
    3. Ex/Mem: Alu Result
    4. A and B
    5. B and C **

12. Which of the following exceptions might be identified on a MIPS-like processor because we change control hazard management from detect and stall to speculate and squash? Note: we are not asking whether the exception is taken, just identified.

    1. Bad opcode
    2. Divide by zero
    3. Data hazard
    4. A and B **
    5. A, B and C

13. What does Amdahl's law say?

  1. Execution time = Instruction count * CPI / MHz
  2. Performance Improvement is limited by the amount the improved feature is used. **
  3. The clock frequency of a processor is determined by the speed of performing an integer addition.
  4. Processor performance approximately doubles every 18 months.
  5. Internet companies stocks valuations approximately double every 18 months.

 

14. How many hazards exist in the following LC2K1 code (make no assumptions about branch prediction or squashing – i.e. assume that branches may be predicted as taken or not taken, and the predictor may be right or wrong)?

add 1 2 2

beq 2 4 3

lw 2 3 10

sw 3 2 6

beq 1 1 -5

halt

    1. 4
    2. 5 **
    3. 6
    4. 7
    5. 8

15. How many clock cycles will be saved when executing the code shown in question 14 if we use detect and forward instead of detect and stall for handling data hazards? Assume that registers 1 through 4 contain values (1,0,2,3) and that branch hazard management uses speculate and squash and that all branches are predicted not taken.
    1. 4
    2. 5
    3. 6
    4. 7
    5. 8 **