EECS 370 Exam 3 16 Nov 2001
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Scott Mahlke or Gary Tyson |
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Honor Code: I have neither given nor received aid on this exam. |
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There are 15 multiple-choice questions, each of equal
value. Each question has one correct
answer. You should mark your answers on the optical grade forms provided. This
is a closed book, closed notes examinations.
Dont forget to copy your answers to compare with the key posted
after the exam.
1.
All cache misses can be divided into these basic types:
a. Component, Compulsory, Compound
b. Component, Conflict, Compulsory
c. Conflict, Component, Capacity
d.
Capacity,
Conflict, Compulsory
e. Capacity, Compulsory, Compound
2.
How many bits of the address are needed to
index into a 4-way set-associative cache with 128 blocks?
a.
5
b. 6
c. 7
d. 8
e. Can't tell from the information
provided in the question.
3. What happens to the tag field as cache associativity increases
(assume that the cache block size and number of cache blocks are unchanged)?
a.
tag
size increases
b. tag size decreases
c. tag bits are shifted left
d. tag bits are shifted right
e. tag remains unchanged
4. Given a 2 level page table with 2K byte
pages, requiring 4 bytes per page table entry.
What are the sizes (in bytes) of the super page table and the page table
for a machine with 32-bit virtual addresses?
a. 2K bytes and 1M bytes
b. 2K bytes and 2M bytes
c. 4K bytes and 4M bytes
d.
16K
bytes and 8M bytes
e. 16K
bytes and 16M bytes
Consider the
following data cache configuration and instruction stream. This information
applies for the next 3 questions.
Cache
configuration: Cache size: 64 bytes
Block size: 8 bytes
Write policy: write-back,
write-allocate
Associativity: 2-way
associative
Replacement policy: LRU
Address information: 8-bit address, byte-addressable
Reference
stream: Ref
1: load to address
0 1 0 0 1 1 1 1
Ref 2:
load to address 0
1 0 1 0 0 1 0
Ref 3:
store to address 0
1 1 1 0 1 1 0
Ref 4:
store to address 0
1 0 1 0 0 0 0
Ref 5:
store to address 1
1 1 1 0 1 1 1
Ref 6:
load to address 0
1 1 1 0 0 1 0
Ref 7:
load to address 1
1 1 1 0 0 0 1
Ref 8:
store to address 0
1 1 1 0 0 1 1
5. How many cache misses occur in the reference stream?
a. 4
b.
5
c. 6
d. 7
e. 8
6. What is the tag field of the
block replaced when reference 6 misses?
a.
010
b. 01010
c. 111
d. 11110
e. Reference 6 is a cache hit
7. How many bytes of data are transferred
to/from memory during the execution of the instruction sequence? Only count those transfers that occur by the
end of reference 8.
a. 44
b. 48
c. 52
d.
56
e. 64
Consider the
following cache configuration and assembly program for the LC2k1 pipelined
datapath that has been extended to contain caches. We will focus exclusively on the data cache here, so you should
assume a perfect instruction cache where all instruction references are hits.
This information applies for the next 3 questions.
Data cache
configuration: Cache size: 8
words
Block size: 2 words
Write policy: write-through,
write-allocate
Associativity: Direct-mapped
Address information: 16-bit, word-addressable addresses
Initial
register values: r1 = 1, r2 = 3, all other registers and memory contain the
value 0.
loop: beq 3
2 exit
lw
3 4 16
lw 3 5 20
add
4 5 6
sw
3 6 24
add
1 3 3
beq
2 2 loop
exit: halt
8. How many data references occur during execution of the LC2K1 code?
a. 3
b. 6
c.
9
d. 12
e. 15
9. How many conflict misses occur during execution of the LC2K1 code?
a. 1
b.
2
c. 3
d. 4
e. 5
10. If the cache access time is 1 cycle and
memory access time is 40 cycles, what is the CPI for the LC2K1 code?
a. Less
than 5
b. Between
5 and 7
c. Between
7 and 9
d. Between
9 and 11
e.
Greater than 11
11.
Suppose you modify the
LC2k1 pipelined datapath discussed in lecture to be superpipelined with 8
stages:IF1, IF2, ID, EX1, EX2, MEM1, MEM2 and WB. As in lecture, the WB stage writes to the register file
before registers are read during decode (i.e. uses transparent flip flops in
the register file). How many data hazard checks (comparators) are necessary in
this design?
a. 6
b.
8
c. 10
d. 12
e. 14
12. Compare the miss rate of a 4-entry TLB and the
cache described in questions 8-10 for the example LC2K1 code shown (assume that
we add virtual memory with a 2048 word page size).
a. TLB miss rate is higher than cache miss rate
b.
TLB miss rate is lower than cache miss rate
c. TLB and cache miss rates are the same
13. Which one of the following events may not
occur when handling a page fault exception in the operating system?
a. Stop the process that had the page
fault
b. Allocate a page of physical memory
to hold the referenced data.
c. Update the page table for the process that had
the page fault
d.
Update
the TLB entry for the process that had the page fault
e. Restart
the process at the instruction that caused the page fault.
14. Which of the following statements is false (only one is)?
a. Virtual address caches do not require a TLB on a hit
b. Physical address caches do require a TLB for fast access
c. The TLB contains a virtual page tag and a physical page number for each entry.
d. The number of entries in the page table is determined by the size of the virtual address.
e.
A page fault occurs on a TLB miss.
15.
For the LC2K1 pipeline
simulator that you wrote for Project 3, suppose you run the test case given
below. You discover that the value in EX/MEM:aluResult
is incorrect before cycle 7 starts.
From cycle 0 through the start of cycle 6, all pipeline registers
contain correct execution results. Which of the following is most likely to be
the error? Assume M[10] = 10 and M[11] = 20. Cycle timing is the same as done
in the assignment (i.e., lw 0 1 10 is written to the IF/ID pipeline register at
the end of cycle 0).
lw
0 1 10
lw
0 2 11
add
2 2 3
add
1 2 4
halt
a. noop insertion problem for lw
0 1 10
b. noop insertion problem for lw
0 2 11
c. forwarding problem from EX/MEM to Execute
d. forwarding problem from MEM/WB to Execute
e.
forwarding
problem from WBEND to Execute