A walk through interrupts on the PPC 823

Review – software viewpoint

Interrupt occurs

Processor saves limited state

SRR0 – Next instruction to be executed when return from interrupt.

SRR1 – Copy of MSR

MSR is modified. Most important is EE bit=0

Processor jumps to the Interrupt Service Routine.

ISR executes.

Needs to save state so that it can put it all back before return from interrupt.

May enable nested interrupts

Does its thing  This is a big step…

Restores state (disables nested interrupts if needed!)

Return from interrupt (rfi instruction)

Details of software viewpoint

How does the ISR know where to branch to?

Table 7.1 indicates the low 5-hex digits of the address.

The IP bit of the MSR (page 6-21) determines the high order bits.

But even then, we need to do
different things for different
interrupt lines.

SIVEC…

So how do we run the right code?

SIVEC holds an 8 bit code which indicates which interrupt was the highest level external interrupt.

Page 12-6.

This can be used to figure out which “line” is the highest priority interrupt.

While a switch statement would work, it is fairly ugly.

Rather we use an indirect branch.

Sample code is on page 12-11

Ok, so we’ve got the software mostly down…

Some issues

Changing the MSR could be important.

We need to be sure we save everything we change.

Don’t forget the condition register.

Not sure what to do to stop the interrupt

We need to clear something somewhere…

So onto hardware.

MPC 823 -- hardware

So how about from the hardware side?

We’ve already seen one special-purpose register (SIVEC)

It turns out there are a few more

SIPEND is a vector of pending interrupts

SIMASK is a vector that allows one to mask out certain interrupts.

SIEL toggles the IRQ interrupts from edge to level

We also have to understand what the different souces of interrupts might do.

Let’s start there.

“External” Interrupts

There are two basic types of external interrupts

Those generated off-chip and those generated on-chip.

Hardware devices you generate on the FPGA will all be off-chip. These use the IRQ interrupts

Timers and other on-chip devices use the LVL interrupts.

Each has somewhat different functionality.

Clearing interrupts

Every interrupt does/should have a single point of reset.

Think of it this way. Somewhere out there is something that is saying “this interrupt is occurring—the device is asking for service”

The ISR needs some way to clear this and indicate that the device is being dealt with.

Doing so remove the interrupt from SIPEND.

Clearing LVL interrupts.

Always level-sensitive.

Probably why named the way they are.

Interrupt source is either CIPR (16-497) or an event bit associated with the interrupt.

You do NOT clear them by writing to SIPEND!

Clearing IRQ interrupts

If the IRQ is edge-triggered the SIPEND register stores the fact that an interrupt has occurred.

The interrupt is cleared at SIPEND in this case

If the IRQ is level-sensitive the interrupt is cleared by direct communication to the I/O device.

When designing I/O devices that generate interrupts keep these things in mind.

Interrupt related registers

We’ve seen SIVEC but there are more…

SIEL

System Interrupt Edge/Level

Determines if IRQ interrupts are level or edge sensitive.

Also controls if IRQ can wake the processor from low-power mode.

SIPEND

Keeps track of the external interrupts that are PENDing.

Used to clear edge-triggered IRQ interrupts.

Can be used rather than SIVEC to figure out what interrupt to service if you really really want to.

SIMASK

Allows certain interrupts to be ignored or masked out.

Is ANDed with SIPEND to determine which interrupts are allowed to interrupt the core and set their value in SIVEC

PPC: Graphical view

Core

IRQ#[0:7]

LVL[0:7]

Flip-

Flops

mux

SIEL

SIPEND

SIMASK

SIVEC

16

16

16

8

8

8

8

IRQ

(core)

A walk through interrupts on the PPC 823

Mark

2004-02-10T11:50:21