// EECS 373 Camera Interface Module for Altera DE2 FPGA
// Code written by: Dimitri Karatsinides
//					Sam Berro
//					Paul Piong
//

module CAM_controller (
				// Inputs from the camera
				PCLK, 
				VSYNC,
				HREF,		
				D,
						
				// Inputs from FPGA switches
				ADDR_IN,
				DATA_IN,
				WR_IN,
				RD_IN,
				RESET,
				
				// TODO: Add stuff to interface with SDRAM
								
				// Outputs to camera
				OEB,
				WEB,
				A,
				
				// Outputs to FPGA
				LED,
				FSM_STATE
				);
	
	input		PCLK, VSYNC, HREF;
	input [3:0] ADDR_IN;
	input [7:0] DATA_IN;
	input		WR_IN, RD_IN, RESET;
	inout [7:0] D;
	
	output reg	OEB, WEB;
	output reg [3:0]A;
	output wire [6:0]LED;
	output wire [2:0]FSM_STATE;
	
	reg [2:0]	state, next_state;
	reg			next_OEB, next_WEB;
	reg [3:0]	next_A;
	reg [7:0]	D_reg, next_D;

	reg [2:0]	cnt_state, next_cnt_state;
	
	parameter IDLE = 3'b000;
	parameter WR_1 = 3'b001;
	parameter WR_2 = 3'b010;
	parameter WR_3 = 3'b011;
	parameter RD_1 = 3'b100;
	parameter RD_2 = 3'b101;
	
	assign FSM_STATE = state[2:0];

	assign LED = (state == IDLE) ? D[6:0] : 7'b0;
	assign D = (state != IDLE) ? D_reg : 8'bZZZZZZZZ;
		
	// Next state logic and some output logic
	always @ *
	begin
		next_state = state;
		next_WEB = WEB;
		next_OEB = OEB;
		next_A = A;
		next_D = D_reg;
		
		case (state)
		IDLE:
			begin
				if (WR_IN && VSYNC)
				begin
					next_OEB = 1'b1;
					next_WEB = 1'b1;
					next_A = ADDR_IN;
					next_D = DATA_IN;
					next_state = WR_1;
				end
				else if (RD_IN && VSYNC)
				begin
					next_OEB = 1'b0;
					next_WEB = 1'b1;
					next_A = ADDR_IN;
					next_state = RD_1;
				end
			end
		WR_1:
			begin
				next_OEB = 1'b1;
				next_WEB = 1'b0;
				next_state = WR_2;
			end
		WR_2:
			begin
				next_OEB = 1'b0;
				next_WEB = 1'b1;
				next_state = WR_3;
			end
		WR_3:
			begin
				next_OEB = 1'b0;
				next_WEB = 1'b1;
				next_D = 8'bZZZZZZZZ; // Put into high-Z mode
				next_state = IDLE;
			end
		RD_1:
			begin
				next_state = RD_2;
			end
		RD_2:
			begin
				// TODO: Latch in data in this state
				next_state = IDLE;
			end
		default:
			next_state = IDLE;
					
		endcase
	end

	always @ (posedge PCLK)
	begin
		if (RESET)
		begin
			state <= IDLE;
			WEB <= 1'b1;
			OEB <= 1'b0;
			A <= 4'b0;
			D_reg <= 8'bZZZZZZZZ; // Put into high-Z mode
		end
		else
		begin
			state <= next_state;
			WEB <= next_WEB;
			OEB <= next_OEB;
			A <= next_A;
			D_reg <= next_D;
		end	
	end

endmodule