Course Information
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DCO Support
jvanlav [at] eecs.umich.edu
Contact Joel VanLaven (staff) for major CAD tool issues.
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Course Catalog
Course Description: VLSI Design I (4 credits)
• Design techniques for rapid implementations of very large-scale integrated (VLSI) circuits, MOS technology and logic
• Structured design
• Design rules, layout procedures
• Design aids: layout, design rule checking, logic and circuit simulation
• Timing and testability
• Architectures for VLSI
• Projects to develop and layout circuits
Course Objectives
This course introduces mask-level integrated circuit design. Correct engineering design methodology is emphasized. Topics covered in lectures include: CMOS processes, mask layout methods and design rules; circuit characterization and performance estimation; design for testability; and CMOS subsystem and system design.
Lab
This is a project-oriented course in which you will design a modest-sized CMOS integrated circuit. Except for the tutorials at the beginning of the semester, no specific lab times are scheduled, and you can work at your convenience. CAEN Labs are open 24 hours a day.
Assignments
The term project involves the design of a 16-bit RISC microprocessor. The initial cell designs (CAD assignments 1 & 2) probably will not be used in the final project and must be done individually. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be your own.
The final project will be done in teams of four or five. The project must be completed, and you must submit a final report in the format specified. Within the constraints of available funding, eligible projects will be fabricated through the MOSIS service. If your project is fabricated, it must be tested; you can get credit for testing it in EECS 579 or as a directed study project. You are encouraged to enter your design in the DAC Student Design Contest.
Prerequisites
EECS 270 and EECS 312. Students are expected to know logic design, transistor-level circuit design (especially static CMOS), and device physics. Some background in computer architecture is helpful (EECS 370), but not required.
Exams
There will be 90 minute (in-class) quizzes approximately every 6 weeks during the semester (2 quizzes total).
Textbooks
Jan Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice Hall, 2003.
We will also be pulling material from the following texts:
N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition, Addison-Wesley, 2005.
Design of High-Performance Microprocessor Circuits, edited by A. Chandrakasan, W. Bowhill, and F. Fox, IEEE Press, 2001.
Another useful circuit design reference is:
D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd edition, McGraw Hill, 2004.
Grading Policy
Homeworks (including project presentation): 10%
CAD assignments: 35%
Quizzes: 25% (12.5% each)
Final project, report, and individual contributions: 30%
Late Policies
CAD and homework assignments will be submitted electronically and are due at 11pm on the due date. Be sure to do your design work in the class directory so that we will have access to it. Do not change the access rights to your class directory. Do not modify submitted files until you get email to say that they have been graded. Late penalties are 20% for each day after the deadline. Note that late penalties are applied only to those portions of the assignment that are finished late. For example, if the schematic and functional verification was completed on time but layout was late, only the layout portion will be subject to the late penalty.