Schedule
| Sunday | Monday | Tuesday | Wednesday | Thursday | Friday | Saturday | |
|---|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | |||
| Sep 2009 | 6 | 7 | 8 No discussion | 9 Lec1 Intro, manufacturing Tut1 7-9pm | 10 | 11 | 12 |
| 13 | 14 Lec2 Design rules and layout | 15 Tut 1.5 | 16 Lec3 CMOS review Cad1 due | 17 | 18 | 19 | |
| 20 | 21 Lec4 Logical effort Hw1 due Cad2 due | 22 | 23 Lec5 Logical effort | 24 | 25 | 26 | |
| 27 | 28 Lec6 Logic styles Hw2 due | 29 | 30 Lec7 Logic styles Cad3 due | 1 | 2 | 3 | |
| Oct 2009 | 4 | 5 Lec8 Adders | 6 | 7 Lec9 Shifters Hw3 due | 8 | 9 | 10 |
| 11 | 12 Lec10 Multipliers | 13 Tut2 in Discussion | 14 Quiz1 Cad4 due | 15 | 16 | 17 | |
| 18 | 19 No class, Fall break | 20 Fall break | 21 Lec11 Power and energy | 22 | 23 | 24 | |
| 25 | 26 Lec12 Dynamic power reduction | 27 Tut 2.5 | 28 Lec13 Leakage power reduction Cad5 due | 29 | 30 | 31 | |
| Nov 2009 | 1 | 2 Charge recovery logic (by Wei-Hsiang) | 3 | 4 Lec14 Timing Cad6 due | 5 | 6 | 7 |
| 8 | 9 Lec15 Latches and registers | 10 | 11 Lec16 Memory core and peripherals Cad7 due | 12 | 13 | 14 | |
| 15 | 16 Lec17 Memory reliability and power Hw4 due | 17 | 18 Lec18 Interconnects Cad8 due | 19 | 20 | 21 | |
| 22 | 23 Lec19 Advanced interconnects | 24 | 25 Quiz2 | 26 Thanksgiving | 27 Thanksgiving | 28 | |
| 29 | 30 Lec20 Design and synthesis | 1 | 2 Lec21 Design for test | 3 | 4 | 5 | |
| Dec 2009 | 6 | 7 Lec22 Clock distribution | 8 | 9 Lec23 Power grid | 10 | 11 | 12 |
| 13 | 14 Final Project Demos Final Project Presentatoin Cad9 due Hw5 due | 15 | 16 | 17 | 18 | 19 | |
| 20 | 21 | 22 | 23 | 24 | 25 | 26 | |
| 27 | 28 | 29 | 30 | 31 |