Analysis & Synthesis report for top
Sun Sep 21 15:20:17 2014
Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis IP Cores Summary
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Parameter Settings for User Entity Instance: AUDIO:audio_inst1
 12. Parameter Settings for User Entity Instance: AUDIO:audio_inst1|clock:c1|altpll:altpll_component
 13. altpll Parameter Settings by Entity Instance
 14. Port Connectivity Checks: "AUDIO:audio_inst1"
 15. Elapsed Time Per Partition
 16. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Sep 21 15:20:16 2014       ;
; Quartus II 64-Bit Version          ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
; Revision Name                      ; top                                         ;
; Top-level Entity Name              ; top                                         ;
; Family                             ; Cyclone II                                  ;
; Total logic elements               ; 61                                          ;
;     Total combinational functions  ; 60                                          ;
;     Dedicated logic registers      ; 45                                          ;
; Total registers                    ; 45                                          ;
; Total pins                         ; 16                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP2C70F896C6       ;                    ;
; Top-level entity name                                                      ; top                ; top                ;
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                            ;
+----------------------------------+-----------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                   ; File Name with Absolute Path                                                                                         ; Library ;
+----------------------------------+-----------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------+---------+
; top.v                            ; yes             ; User Verilog HDL File       ; //engin-labs.m.storage.umich.edu/kurzerjo/windat.v2/Desktop/EECS_452_Labs/Fall14/Lab4/Lab4_Files/PartA/top.v         ;         ;
; clock.v                          ; yes             ; User Wizard-Generated File  ; //engin-labs.m.storage.umich.edu/kurzerjo/windat.v2/Desktop/EECS_452_Labs/Fall14/Lab4/Lab4_Files/PartA/clock.v       ;         ;
; Reset_Delay.v                    ; yes             ; User Verilog HDL File       ; //engin-labs.m.storage.umich.edu/kurzerjo/windat.v2/Desktop/EECS_452_Labs/Fall14/Lab4/Lab4_Files/PartA/Reset_Delay.v ;         ;
; AUDIO.v                          ; yes             ; User Verilog HDL File       ; //engin-labs.m.storage.umich.edu/kurzerjo/windat.v2/Desktop/EECS_452_Labs/Fall14/Lab4/Lab4_Files/PartA/AUDIO.v       ;         ;
; altpll.tdf                       ; yes             ; Megafunction                ; c:/sw/altera-13.0/quartus/libraries/megafunctions/altpll.tdf                                                         ;         ;
; aglobal130.inc                   ; yes             ; Megafunction                ; c:/sw/altera-13.0/quartus/libraries/megafunctions/aglobal130.inc                                                     ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                ; c:/sw/altera-13.0/quartus/libraries/megafunctions/stratix_pll.inc                                                    ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                ; c:/sw/altera-13.0/quartus/libraries/megafunctions/stratixii_pll.inc                                                  ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                ; c:/sw/altera-13.0/quartus/libraries/megafunctions/cycloneii_pll.inc                                                  ;         ;
+----------------------------------+-----------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 61      ;
;                                             ;         ;
; Total combinational functions               ; 60      ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 16      ;
;     -- 3 input functions                    ; 9       ;
;     -- <=2 input functions                  ; 35      ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 34      ;
;     -- arithmetic mode                      ; 26      ;
;                                             ;         ;
; Total registers                             ; 45      ;
;     -- Dedicated logic registers            ; 45      ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 16      ;
; Embedded Multiplier 9-bit elements          ; 0       ;
; Total PLLs                                  ; 1       ;
;     -- PLLs                                 ; 1       ;
;                                             ;         ;
; Maximum fan-out node                        ; iCLK_50 ;
; Maximum fan-out                             ; 22      ;
; Total fan-out                               ; 300     ;
; Average fan-out                             ; 2.46    ;
+---------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                     ;
+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------+--------------+
; Compilation Hierarchy Node         ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                     ; Library Name ;
+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------+--------------+
; |top                               ; 60 (2)            ; 45 (3)       ; 0           ; 0            ; 0       ; 0         ; 16   ; 0            ; |top                                                    ;              ;
;    |AUDIO:audio_inst1|             ; 58 (30)           ; 42 (21)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|AUDIO:audio_inst1                                  ;              ;
;       |Reset_Delay:r0|             ; 28 (28)           ; 21 (21)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|AUDIO:audio_inst1|Reset_Delay:r0                   ;              ;
;       |clock:c1|                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|AUDIO:audio_inst1|clock:c1                         ;              ;
;          |altpll:altpll_component| ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|AUDIO:audio_inst1|clock:c1|altpll:altpll_component ;              ;
+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                            ;
+--------+--------------+---------+--------------+--------------+---------------------------------+----------------------------------------------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                 ; IP Include File                                                                                                ;
+--------+--------------+---------+--------------+--------------+---------------------------------+----------------------------------------------------------------------------------------------------------------+
; Altera ; ALTPLL       ; N/A     ; N/A          ; N/A          ; |top|AUDIO:audio_inst1|clock:c1 ; //engin-labs.m.storage.umich.edu/kurzerjo/windat.v2/Desktop/EECS_452_Labs/Fall14/Lab4/Lab4_Files/PartA/clock.v ;
+--------+--------------+---------+--------------+--------------+---------------------------------+----------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; DataOut[0..12]                         ; Stuck at GND due to stuck port data_in ;
; AUDIO:audio_inst1|BCK_DIV[3]           ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 14 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 45    ;
; Number of registers using Synchronous Clear  ; 9     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: AUDIO:audio_inst1 ;
+----------------+----------+------------------------------------+
; Parameter Name ; Value    ; Type                               ;
+----------------+----------+------------------------------------+
; REF_CLK        ; 18432000 ; Signed Integer                     ;
; SAMPLE_RATE    ; 48000    ; Signed Integer                     ;
; CHANNEL_NUM    ; 2        ; Signed Integer                     ;
+----------------+----------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: AUDIO:audio_inst1|clock:c1|altpll:altpll_component ;
+-------------------------------+-------------------------+---------------------------------------+
; Parameter Name                ; Value                   ; Type                                  ;
+-------------------------------+-------------------------+---------------------------------------+
; OPERATION_MODE                ; NORMAL                  ; Untyped                               ;
; PLL_TYPE                      ; AUTO                    ; Untyped                               ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=clock ; Untyped                               ;
; QUALIFY_CONF_DONE             ; OFF                     ; Untyped                               ;
; COMPENSATE_CLOCK              ; CLK0                    ; Untyped                               ;
; SCAN_CHAIN                    ; LONG                    ; Untyped                               ;
; PRIMARY_CLOCK                 ; INCLK0                  ; Untyped                               ;
; INCLK0_INPUT_FREQUENCY        ; 20000                   ; Signed Integer                        ;
; INCLK1_INPUT_FREQUENCY        ; 0                       ; Untyped                               ;
; GATE_LOCK_SIGNAL              ; NO                      ; Untyped                               ;
; GATE_LOCK_COUNTER             ; 0                       ; Untyped                               ;
; LOCK_HIGH                     ; 1                       ; Untyped                               ;
; LOCK_LOW                      ; 1                       ; Untyped                               ;
; VALID_LOCK_MULTIPLIER         ; 1                       ; Untyped                               ;
; INVALID_LOCK_MULTIPLIER       ; 5                       ; Untyped                               ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                     ; Untyped                               ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                     ; Untyped                               ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                     ; Untyped                               ;
; SKIP_VCO                      ; OFF                     ; Untyped                               ;
; SWITCH_OVER_COUNTER           ; 0                       ; Untyped                               ;
; SWITCH_OVER_TYPE              ; AUTO                    ; Untyped                               ;
; FEEDBACK_SOURCE               ; EXTCLK0                 ; Untyped                               ;
; BANDWIDTH                     ; 0                       ; Untyped                               ;
; BANDWIDTH_TYPE                ; AUTO                    ; Untyped                               ;
; SPREAD_FREQUENCY              ; 0                       ; Untyped                               ;
; DOWN_SPREAD                   ; 0                       ; Untyped                               ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                     ; Untyped                               ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                     ; Untyped                               ;
; CLK9_MULTIPLY_BY              ; 0                       ; Untyped                               ;
; CLK8_MULTIPLY_BY              ; 0                       ; Untyped                               ;
; CLK7_MULTIPLY_BY              ; 0                       ; Untyped                               ;
; CLK6_MULTIPLY_BY              ; 0                       ; Untyped                               ;
; CLK5_MULTIPLY_BY              ; 1                       ; Untyped                               ;
; CLK4_MULTIPLY_BY              ; 1                       ; Untyped                               ;
; CLK3_MULTIPLY_BY              ; 1                       ; Untyped                               ;
; CLK2_MULTIPLY_BY              ; 1                       ; Untyped                               ;
; CLK1_MULTIPLY_BY              ; 1                       ; Untyped                               ;
; CLK0_MULTIPLY_BY              ; 1152                    ; Signed Integer                        ;
; CLK9_DIVIDE_BY                ; 0                       ; Untyped                               ;
; CLK8_DIVIDE_BY                ; 0                       ; Untyped                               ;
; CLK7_DIVIDE_BY                ; 0                       ; Untyped                               ;
; CLK6_DIVIDE_BY                ; 0                       ; Untyped                               ;
; CLK5_DIVIDE_BY                ; 1                       ; Untyped                               ;
; CLK4_DIVIDE_BY                ; 1                       ; Untyped                               ;
; CLK3_DIVIDE_BY                ; 1                       ; Untyped                               ;
; CLK2_DIVIDE_BY                ; 1                       ; Untyped                               ;
; CLK1_DIVIDE_BY                ; 1                       ; Untyped                               ;
; CLK0_DIVIDE_BY                ; 3125                    ; Signed Integer                        ;
; CLK9_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK8_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK7_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK6_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK5_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK4_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK3_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK2_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK1_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK0_PHASE_SHIFT              ; 0                       ; Untyped                               ;
; CLK5_TIME_DELAY               ; 0                       ; Untyped                               ;
; CLK4_TIME_DELAY               ; 0                       ; Untyped                               ;
; CLK3_TIME_DELAY               ; 0                       ; Untyped                               ;
; CLK2_TIME_DELAY               ; 0                       ; Untyped                               ;
; CLK1_TIME_DELAY               ; 0                       ; Untyped                               ;
; CLK0_TIME_DELAY               ; 0                       ; Untyped                               ;
; CLK9_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK8_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK7_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK6_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK5_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK4_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK3_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK2_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK1_DUTY_CYCLE               ; 50                      ; Untyped                               ;
; CLK0_DUTY_CYCLE               ; 50                      ; Signed Integer                        ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                               ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                               ;
; LOCK_WINDOW_UI                ;  0.05                   ; Untyped                               ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                  ; Untyped                               ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                  ; Untyped                               ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                  ; Untyped                               ;
; DPA_MULTIPLY_BY               ; 0                       ; Untyped                               ;
; DPA_DIVIDE_BY                 ; 1                       ; Untyped                               ;
; DPA_DIVIDER                   ; 0                       ; Untyped                               ;
; EXTCLK3_MULTIPLY_BY           ; 1                       ; Untyped                               ;
; EXTCLK2_MULTIPLY_BY           ; 1                       ; Untyped                               ;
; EXTCLK1_MULTIPLY_BY           ; 1                       ; Untyped                               ;
; EXTCLK0_MULTIPLY_BY           ; 1                       ; Untyped                               ;
; EXTCLK3_DIVIDE_BY             ; 1                       ; Untyped                               ;
; EXTCLK2_DIVIDE_BY             ; 1                       ; Untyped                               ;
; EXTCLK1_DIVIDE_BY             ; 1                       ; Untyped                               ;
; EXTCLK0_DIVIDE_BY             ; 1                       ; Untyped                               ;
; EXTCLK3_PHASE_SHIFT           ; 0                       ; Untyped                               ;
; EXTCLK2_PHASE_SHIFT           ; 0                       ; Untyped                               ;
; EXTCLK1_PHASE_SHIFT           ; 0                       ; Untyped                               ;
; EXTCLK0_PHASE_SHIFT           ; 0                       ; Untyped                               ;
; EXTCLK3_TIME_DELAY            ; 0                       ; Untyped                               ;
; EXTCLK2_TIME_DELAY            ; 0                       ; Untyped                               ;
; EXTCLK1_TIME_DELAY            ; 0                       ; Untyped                               ;
; EXTCLK0_TIME_DELAY            ; 0                       ; Untyped                               ;
; EXTCLK3_DUTY_CYCLE            ; 50                      ; Untyped                               ;
; EXTCLK2_DUTY_CYCLE            ; 50                      ; Untyped                               ;
; EXTCLK1_DUTY_CYCLE            ; 50                      ; Untyped                               ;
; EXTCLK0_DUTY_CYCLE            ; 50                      ; Untyped                               ;
; VCO_MULTIPLY_BY               ; 0                       ; Untyped                               ;
; VCO_DIVIDE_BY                 ; 0                       ; Untyped                               ;
; SCLKOUT0_PHASE_SHIFT          ; 0                       ; Untyped                               ;
; SCLKOUT1_PHASE_SHIFT          ; 0                       ; Untyped                               ;
; VCO_MIN                       ; 0                       ; Untyped                               ;
; VCO_MAX                       ; 0                       ; Untyped                               ;
; VCO_CENTER                    ; 0                       ; Untyped                               ;
; PFD_MIN                       ; 0                       ; Untyped                               ;
; PFD_MAX                       ; 0                       ; Untyped                               ;
; M_INITIAL                     ; 0                       ; Untyped                               ;
; M                             ; 0                       ; Untyped                               ;
; N                             ; 1                       ; Untyped                               ;
; M2                            ; 1                       ; Untyped                               ;
; N2                            ; 1                       ; Untyped                               ;
; SS                            ; 1                       ; Untyped                               ;
; C0_HIGH                       ; 0                       ; Untyped                               ;
; C1_HIGH                       ; 0                       ; Untyped                               ;
; C2_HIGH                       ; 0                       ; Untyped                               ;
; C3_HIGH                       ; 0                       ; Untyped                               ;
; C4_HIGH                       ; 0                       ; Untyped                               ;
; C5_HIGH                       ; 0                       ; Untyped                               ;
; C6_HIGH                       ; 0                       ; Untyped                               ;
; C7_HIGH                       ; 0                       ; Untyped                               ;
; C8_HIGH                       ; 0                       ; Untyped                               ;
; C9_HIGH                       ; 0                       ; Untyped                               ;
; C0_LOW                        ; 0                       ; Untyped                               ;
; C1_LOW                        ; 0                       ; Untyped                               ;
; C2_LOW                        ; 0                       ; Untyped                               ;
; C3_LOW                        ; 0                       ; Untyped                               ;
; C4_LOW                        ; 0                       ; Untyped                               ;
; C5_LOW                        ; 0                       ; Untyped                               ;
; C6_LOW                        ; 0                       ; Untyped                               ;
; C7_LOW                        ; 0                       ; Untyped                               ;
; C8_LOW                        ; 0                       ; Untyped                               ;
; C9_LOW                        ; 0                       ; Untyped                               ;
; C0_INITIAL                    ; 0                       ; Untyped                               ;
; C1_INITIAL                    ; 0                       ; Untyped                               ;
; C2_INITIAL                    ; 0                       ; Untyped                               ;
; C3_INITIAL                    ; 0                       ; Untyped                               ;
; C4_INITIAL                    ; 0                       ; Untyped                               ;
; C5_INITIAL                    ; 0                       ; Untyped                               ;
; C6_INITIAL                    ; 0                       ; Untyped                               ;
; C7_INITIAL                    ; 0                       ; Untyped                               ;
; C8_INITIAL                    ; 0                       ; Untyped                               ;
; C9_INITIAL                    ; 0                       ; Untyped                               ;
; C0_MODE                       ; BYPASS                  ; Untyped                               ;
; C1_MODE                       ; BYPASS                  ; Untyped                               ;
; C2_MODE                       ; BYPASS                  ; Untyped                               ;
; C3_MODE                       ; BYPASS                  ; Untyped                               ;
; C4_MODE                       ; BYPASS                  ; Untyped                               ;
; C5_MODE                       ; BYPASS                  ; Untyped                               ;
; C6_MODE                       ; BYPASS                  ; Untyped                               ;
; C7_MODE                       ; BYPASS                  ; Untyped                               ;
; C8_MODE                       ; BYPASS                  ; Untyped                               ;
; C9_MODE                       ; BYPASS                  ; Untyped                               ;
; C0_PH                         ; 0                       ; Untyped                               ;
; C1_PH                         ; 0                       ; Untyped                               ;
; C2_PH                         ; 0                       ; Untyped                               ;
; C3_PH                         ; 0                       ; Untyped                               ;
; C4_PH                         ; 0                       ; Untyped                               ;
; C5_PH                         ; 0                       ; Untyped                               ;
; C6_PH                         ; 0                       ; Untyped                               ;
; C7_PH                         ; 0                       ; Untyped                               ;
; C8_PH                         ; 0                       ; Untyped                               ;
; C9_PH                         ; 0                       ; Untyped                               ;
; L0_HIGH                       ; 1                       ; Untyped                               ;
; L1_HIGH                       ; 1                       ; Untyped                               ;
; G0_HIGH                       ; 1                       ; Untyped                               ;
; G1_HIGH                       ; 1                       ; Untyped                               ;
; G2_HIGH                       ; 1                       ; Untyped                               ;
; G3_HIGH                       ; 1                       ; Untyped                               ;
; E0_HIGH                       ; 1                       ; Untyped                               ;
; E1_HIGH                       ; 1                       ; Untyped                               ;
; E2_HIGH                       ; 1                       ; Untyped                               ;
; E3_HIGH                       ; 1                       ; Untyped                               ;
; L0_LOW                        ; 1                       ; Untyped                               ;
; L1_LOW                        ; 1                       ; Untyped                               ;
; G0_LOW                        ; 1                       ; Untyped                               ;
; G1_LOW                        ; 1                       ; Untyped                               ;
; G2_LOW                        ; 1                       ; Untyped                               ;
; G3_LOW                        ; 1                       ; Untyped                               ;
; E0_LOW                        ; 1                       ; Untyped                               ;
; E1_LOW                        ; 1                       ; Untyped                               ;
; E2_LOW                        ; 1                       ; Untyped                               ;
; E3_LOW                        ; 1                       ; Untyped                               ;
; L0_INITIAL                    ; 1                       ; Untyped                               ;
; L1_INITIAL                    ; 1                       ; Untyped                               ;
; G0_INITIAL                    ; 1                       ; Untyped                               ;
; G1_INITIAL                    ; 1                       ; Untyped                               ;
; G2_INITIAL                    ; 1                       ; Untyped                               ;
; G3_INITIAL                    ; 1                       ; Untyped                               ;
; E0_INITIAL                    ; 1                       ; Untyped                               ;
; E1_INITIAL                    ; 1                       ; Untyped                               ;
; E2_INITIAL                    ; 1                       ; Untyped                               ;
; E3_INITIAL                    ; 1                       ; Untyped                               ;
; L0_MODE                       ; BYPASS                  ; Untyped                               ;
; L1_MODE                       ; BYPASS                  ; Untyped                               ;
; G0_MODE                       ; BYPASS                  ; Untyped                               ;
; G1_MODE                       ; BYPASS                  ; Untyped                               ;
; G2_MODE                       ; BYPASS                  ; Untyped                               ;
; G3_MODE                       ; BYPASS                  ; Untyped                               ;
; E0_MODE                       ; BYPASS                  ; Untyped                               ;
; E1_MODE                       ; BYPASS                  ; Untyped                               ;
; E2_MODE                       ; BYPASS                  ; Untyped                               ;
; E3_MODE                       ; BYPASS                  ; Untyped                               ;
; L0_PH                         ; 0                       ; Untyped                               ;
; L1_PH                         ; 0                       ; Untyped                               ;
; G0_PH                         ; 0                       ; Untyped                               ;
; G1_PH                         ; 0                       ; Untyped                               ;
; G2_PH                         ; 0                       ; Untyped                               ;
; G3_PH                         ; 0                       ; Untyped                               ;
; E0_PH                         ; 0                       ; Untyped                               ;
; E1_PH                         ; 0                       ; Untyped                               ;
; E2_PH                         ; 0                       ; Untyped                               ;
; E3_PH                         ; 0                       ; Untyped                               ;
; M_PH                          ; 0                       ; Untyped                               ;
; C1_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C2_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C3_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C4_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C5_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C6_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C7_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C8_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; C9_USE_CASC_IN                ; OFF                     ; Untyped                               ;
; CLK0_COUNTER                  ; G0                      ; Untyped                               ;
; CLK1_COUNTER                  ; G0                      ; Untyped                               ;
; CLK2_COUNTER                  ; G0                      ; Untyped                               ;
; CLK3_COUNTER                  ; G0                      ; Untyped                               ;
; CLK4_COUNTER                  ; G0                      ; Untyped                               ;
; CLK5_COUNTER                  ; G0                      ; Untyped                               ;
; CLK6_COUNTER                  ; E0                      ; Untyped                               ;
; CLK7_COUNTER                  ; E1                      ; Untyped                               ;
; CLK8_COUNTER                  ; E2                      ; Untyped                               ;
; CLK9_COUNTER                  ; E3                      ; Untyped                               ;
; L0_TIME_DELAY                 ; 0                       ; Untyped                               ;
; L1_TIME_DELAY                 ; 0                       ; Untyped                               ;
; G0_TIME_DELAY                 ; 0                       ; Untyped                               ;
; G1_TIME_DELAY                 ; 0                       ; Untyped                               ;
; G2_TIME_DELAY                 ; 0                       ; Untyped                               ;
; G3_TIME_DELAY                 ; 0                       ; Untyped                               ;
; E0_TIME_DELAY                 ; 0                       ; Untyped                               ;
; E1_TIME_DELAY                 ; 0                       ; Untyped                               ;
; E2_TIME_DELAY                 ; 0                       ; Untyped                               ;
; E3_TIME_DELAY                 ; 0                       ; Untyped                               ;
; M_TIME_DELAY                  ; 0                       ; Untyped                               ;
; N_TIME_DELAY                  ; 0                       ; Untyped                               ;
; EXTCLK3_COUNTER               ; E3                      ; Untyped                               ;
; EXTCLK2_COUNTER               ; E2                      ; Untyped                               ;
; EXTCLK1_COUNTER               ; E1                      ; Untyped                               ;
; EXTCLK0_COUNTER               ; E0                      ; Untyped                               ;
; ENABLE0_COUNTER               ; L0                      ; Untyped                               ;
; ENABLE1_COUNTER               ; L0                      ; Untyped                               ;
; CHARGE_PUMP_CURRENT           ; 2                       ; Untyped                               ;
; LOOP_FILTER_R                 ;  1.000000               ; Untyped                               ;
; LOOP_FILTER_C                 ; 5                       ; Untyped                               ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                    ; Untyped                               ;
; LOOP_FILTER_R_BITS            ; 9999                    ; Untyped                               ;
; LOOP_FILTER_C_BITS            ; 9999                    ; Untyped                               ;
; VCO_POST_SCALE                ; 0                       ; Untyped                               ;
; CLK2_OUTPUT_FREQUENCY         ; 0                       ; Untyped                               ;
; CLK1_OUTPUT_FREQUENCY         ; 0                       ; Untyped                               ;
; CLK0_OUTPUT_FREQUENCY         ; 0                       ; Untyped                               ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II              ; Untyped                               ;
; PORT_CLKENA0                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKENA1                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKENA2                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKENA3                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKENA4                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKENA5                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_EXTCLK0                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_EXTCLK1                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_EXTCLK2                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_EXTCLK3                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKBAD0                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKBAD1                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK0                     ; PORT_USED               ; Untyped                               ;
; PORT_CLK1                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK2                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK3                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK4                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK5                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK6                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK7                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK8                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLK9                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANDATA                 ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANDATAOUT              ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANDONE                 ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKLOSS                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_INCLK1                   ; PORT_UNUSED             ; Untyped                               ;
; PORT_INCLK0                   ; PORT_USED               ; Untyped                               ;
; PORT_FBIN                     ; PORT_UNUSED             ; Untyped                               ;
; PORT_PLLENA                   ; PORT_UNUSED             ; Untyped                               ;
; PORT_CLKSWITCH                ; PORT_UNUSED             ; Untyped                               ;
; PORT_ARESET                   ; PORT_USED               ; Untyped                               ;
; PORT_PFDENA                   ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANCLK                  ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANACLR                 ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANREAD                 ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANWRITE                ; PORT_UNUSED             ; Untyped                               ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_LOCKED                   ; PORT_UNUSED             ; Untyped                               ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED             ; Untyped                               ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_PHASEDONE                ; PORT_UNUSED             ; Untyped                               ;
; PORT_PHASESTEP                ; PORT_UNUSED             ; Untyped                               ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED             ; Untyped                               ;
; PORT_SCANCLKENA               ; PORT_UNUSED             ; Untyped                               ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED             ; Untyped                               ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY       ; Untyped                               ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY       ; Untyped                               ;
; M_TEST_SOURCE                 ; 5                       ; Untyped                               ;
; C0_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C1_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C2_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C3_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C4_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C5_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C6_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C7_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C8_TEST_SOURCE                ; 5                       ; Untyped                               ;
; C9_TEST_SOURCE                ; 5                       ; Untyped                               ;
; CBXI_PARAMETER                ; NOTHING                 ; Untyped                               ;
; VCO_FREQUENCY_CONTROL         ; AUTO                    ; Untyped                               ;
; VCO_PHASE_SHIFT_STEP          ; 0                       ; Untyped                               ;
; WIDTH_CLOCK                   ; 6                       ; Untyped                               ;
; WIDTH_PHASECOUNTERSELECT      ; 4                       ; Untyped                               ;
; USING_FBMIMICBIDIR_PORT       ; OFF                     ; Untyped                               ;
; DEVICE_FAMILY                 ; Cyclone II              ; Untyped                               ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                  ; Untyped                               ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                     ; Untyped                               ;
; AUTO_CARRY_CHAINS             ; ON                      ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS          ; OFF                     ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS           ; ON                      ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS        ; OFF                     ; IGNORE_CASCADE                        ;
+-------------------------------+-------------------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                       ;
+-------------------------------+----------------------------------------------------+
; Name                          ; Value                                              ;
+-------------------------------+----------------------------------------------------+
; Number of entity instances    ; 1                                                  ;
; Entity Instance               ; AUDIO:audio_inst1|clock:c1|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                             ;
;     -- PLL_TYPE               ; AUTO                                               ;
;     -- PRIMARY_CLOCK          ; INCLK0                                             ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                              ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                  ;
;     -- VCO_MULTIPLY_BY        ; 0                                                  ;
;     -- VCO_DIVIDE_BY          ; 0                                                  ;
+-------------------------------+----------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "AUDIO:audio_inst1"                                                                         ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                             ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; oADC[12..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    Info: Processing started: Sun Sep 21 15:20:11 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Warning (10275): Verilog HDL Module Instantiation warning at top.v(53): ignored dangling comma in List of Port Connections
Info (12021): Found 1 design units, including 1 entities, in source file top.v
    Info (12023): Found entity 1: top
Warning (12019): Can't analyze file -- file DDS.v is missing
Info (12021): Found 1 design units, including 1 entities, in source file clock.v
    Info (12023): Found entity 1: clock
Info (12021): Found 1 design units, including 1 entities, in source file reset_delay.v
    Info (12023): Found entity 1: Reset_Delay
Warning (10274): Verilog HDL macro warning at AUDIO.v(2): overriding existing definition for macro "DATA_WIDTH", which was defined in "top.v", line 2
Warning (10238): Verilog Module Declaration warning at AUDIO.v(19): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "AUDIO"
Info (12021): Found 1 design units, including 1 entities, in source file audio.v
    Info (12023): Found entity 1: AUDIO
Warning (10236): Verilog HDL Implicit Net warning at AUDIO.v(65): created implicit net for "iRST_N"
Info (12127): Elaborating entity "top" for the top level hierarchy
Info (12128): Elaborating entity "AUDIO" for hierarchy "AUDIO:audio_inst1"
Warning (10230): Verilog HDL assignment warning at AUDIO.v(96): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at AUDIO.v(117): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at AUDIO.v(129): truncated value with size 32 to match size of target (4)
Warning (10665): Bidirectional port "AUD_DACLRCK" at AUDIO.v(42) has a one-way connection to bidirectional port "AUD_ADCLRCK"
Info (12128): Elaborating entity "Reset_Delay" for hierarchy "AUDIO:audio_inst1|Reset_Delay:r0"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(10): truncated value with size 32 to match size of target (20)
Info (12128): Elaborating entity "clock" for hierarchy "AUDIO:audio_inst1|clock:c1"
Info (12128): Elaborating entity "altpll" for hierarchy "AUDIO:audio_inst1|clock:c1|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "AUDIO:audio_inst1|clock:c1|altpll:altpll_component"
Info (12133): Instantiated megafunction "AUDIO:audio_inst1|clock:c1|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "3125"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1152"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=clock"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_USED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "AUD_DACLRCK" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "AUD_BCLK" and its non-tri-state driver.
Info (13060): One or more bidirs are fed by always enabled tri-state buffers
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "AUD_DACLRCK" is moved to its source
    Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidir "AUD_BCLK" is moved to its source
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "AUDIO:audio_inst1|AUD_ADCLRCK~synth"
    Warning (13010): Node "AUD_DACLRCK~synth"
    Warning (13010): Node "AUD_BCLK~synth"
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 9 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "iSW[0]"
    Warning (15610): No output dependent on input pin "iSW[1]"
    Warning (15610): No output dependent on input pin "iSW[2]"
    Warning (15610): No output dependent on input pin "iSW[3]"
    Warning (15610): No output dependent on input pin "iSW[4]"
    Warning (15610): No output dependent on input pin "iSW[5]"
    Warning (15610): No output dependent on input pin "iSW[6]"
    Warning (15610): No output dependent on input pin "iSW[7]"
    Warning (15610): No output dependent on input pin "iSW[8]"
Info (21057): Implemented 78 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 11 input pins
    Info (21059): Implemented 2 output pins
    Info (21060): Implemented 3 bidirectional pins
    Info (21061): Implemented 61 logic cells
    Info (21065): Implemented 1 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 27 warnings
    Info: Peak virtual memory: 488 megabytes
    Info: Processing ended: Sun Sep 21 15:20:17 2014
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:02


