/* ######################################################################  
 *                                                                            
 *                           RAppID                                      
 *     Rapid Application Initialization and Documentation Tool            
 *                     freescale Virtual Garage                              
 *                   MPC5554 Configuration Tool                             
 *          Automatically Generated Initialization Code                      
 *                                                                          
 *                                                                          
 * #######################################################################  
 *                                                                          
 *  Project Name: base   
 *                                                                          
 *  Project File: base.mat           
 *                                                                          
 *  Revision Number: 1.85   
 *                          
 *  Tool Version: 1.1.1   
 *                          
 *  Target Compiler: metrowerks   
 *                          
 *  Target Part: 5554      
 *                          
 *  Part Errata Fixes: None  
 *                          
 *  Project Last Save Date: 25-Sep-2008 20:48:19   
 *                          
 *  FunctionName::eqadc_init::FunctionName 
 *                          
 *  Date : 25-Sep-2008  Time : 20:48:27.503
 *
 * ####################################################################### */

/* ################### EQADC Configuration Table ##########################
 * 
 *   This table shows the initilized modes of the Queue's . 
 *   ___________________________________________________________________
 *  |Queue #  |  Mode        | Trigger           | Data Xfr CFIFO/RFIFO |
 *  --------------------------------------------------------------------
 *  |   0     | Single Scan  |  Software Trigger |    DMA/DMA           |
 *  --------------------------------------------------------------------
 *  |   1     |  Disabled    |                   |       /              |
 *  --------------------------------------------------------------------
 *  |   2     |  Disabled    |                   |       /              |
 *  --------------------------------------------------------------------
 *  |   3     |  Disabled    |                   |       /              |
 *  --------------------------------------------------------------------
 *  |   4     |  Disabled    |                   |       /              |
 *  --------------------------------------------------------------------
 *  |   5     |  Disabled    |                   |       /              |
 *  |_________|______________|___________________|______________________|
 * 
 * ######################################################################## */

/* ******************  Dependent Include files Here ********************** */
#include "mpc5554.h"
#include "eqadc_init_hdr.h"

/* ************************** Pragma Section ************************** */

vuint32_t CQUEUE0[1];                   /* CFIFO 0 Queue Variable declaration*/
vuint32_t CQUEUE1[1];                   /* CFIFO 1 Queue Variable declaration*/
vuint32_t CQUEUE2[1];                   /* CFIFO 2 Queue Variable declaration*/
vuint32_t CQUEUE3[1];                   /* CFIFO 3 Queue Variable declaration*/
vuint32_t CQUEUE4[1];                   /* CFIFO 4 Queue Variable declaration*/
vuint32_t CQUEUE5[1];                   /* CFIFO 5 Queue Variable declaration*/

vuint16_t RQUEUE0[1];                   /* RFIFO 0 Queue Variable declaration*/
vuint16_t RQUEUE1[1];                   /* RFIFO 1 Queue Variable declaration*/
vuint16_t RQUEUE2[1];                   /* RFIFO 2 Queue Variable declaration*/
vuint16_t RQUEUE3[1];                   /* RFIFO 3 Queue Variable declaration*/
vuint16_t RQUEUE4[1];                   /* RFIFO 4 Queue Variable declaration*/
vuint16_t RQUEUE5[1];                   /* RFIFO 5 Queue Variable declaration*/

/* ********************* Initialization Function ********************* */
void eqadc_init_fcn(void)
{
  CQUEUE0[0] = 0x80040100;

  /* EQADC Module Configuration Register (EQADC_MCR) */
  EQADC.MCR.R = 0x00000000;             /* EQADC SSI is Disabled */
  /* Debug Mode Disabled */

  /* EQADC NULL Message Send Format Register (EQADC_NMSFR) */
  EQADC.NMSFR.R = 0x0000000;            /* Null Message Format */

  /* EQADC External Trigger Digital Filter Register (EQADC_ETDFR) */
  EQADC.ETDFR.R = 0x00000000;           /* Digital Filter Length = 2 */

  /* EQADC CFIFO Control Register 0 (EQADC_CFCR0)  CFIFO-0 */
  EQADC.CFCR[0].R = 0x0010;             /* Single Scan Enable Bit - 0 */
  /* CFIFO Invalidate Bit -0 */
  /* CFIFO Operation Mode - Software Triggered */
  /* Trigger - Software Triggered, Single Scan Mode */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR0 */
  EQADC.IDCR[0].R = 0x0000;             /* NonCoherency Interrupt is : (0) */
  /* Trigger Overrun Interrupt is : (0) */
  /* Pause Interrupt is : (0) */
  /* End Of Queue Interrupt is : (0) */
  /* CFIFO Underflow Interrupt is : (0) */
  /* CFIFO Fill Enable is : (0) */
  /* CFIFO Fill Select : (0) Manual Mode */
  /* RFIFO Overflow Interrupt is : (0) */
  /* RFIFO Drain is : (0) */
  /* RFIFO Drain Select is : (0) */

  /* EQADC ADC Time Stamp Control Register (ADC_TSCR) */
  /*     ADC_TSCR  = 0x0000;       Bits 12-15 Clock Divide Factor :   0  */
  EQADC.CFPR[0].B.CFPUSH = 0x00000002; /* Initialize the Time Stamp Control Register 0    */

  /* EQADC ADC Time Base Counter Register (ADC_TBCR) - Initialize to 0x0000 */
  /*     ADC_TBCR  = 0x0000;       Time Base Counter Value = 0 */
  EQADC.CFPR[0].B.CFPUSH = 0x00000003; /* Initialize the Time Base Counter Register 0 */

  /* EQADC ADC0 Control Register (ADC0_CR) Enabel ADC0 */
  /*     ADC0_CR  = 0x801F;          Bits 11-15 Clock Prescalar : 64  */
  /* Bit 4 External Mux Enable : Disabled (0)           */
  /* Bit 0 ADC0 Enable ADC0 Ready to Start : Enabled (1)  */
  EQADC.CFPR[0].B.CFPUSH = 0x00801F01; /* Initialize the ADC Control Register 0  */

  /* EQADC ADC1 Control Register (ADC1_CR) Enabel ADC1 */
  /*     ADC1_CR  = 0x801F;          Bits 11-15 Clock Prescalar : 64  */
  /* Bit 4 External Mux Enable : Disabled (0) */
  /* Bit 0 Enable ADC0 Ready to Start : Enabled (1) */
  EQADC.CFPR[0].B.CFPUSH = 0x82801F01; /* Initialize the ADC Control Register 1  */

  EQADC.CFCR[0].B.SSE = 0x01;           /* Trigger the CFIFO0 to configure ADCx's */

  while(EQADC.CFSR.B.CFS0 == 0x3 ){ }   /* Wait for Triggered State to end so we know queue is done. */

  EQADC.FISR[0].B.EOQF = 0x01;          /* Clear the end of queue flag for the configuration command sets. */

  EQADC.CFCR[0].R = 0x0000;             /* Disable the queue in preparation for queue mode change. */

  while(EQADC.CFSR.B.CFS0 != 0x0 ){ }   /* Wait for queue to go to IDLE before setting mode to user setting. */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR0  */
  EQADC.IDCR[0].R = 0x0303;             /* NonCoherency Interrupt is : Disabled (0)  */
  /* Trigger Overrun Interrupt is :Disabled (0)  */
  /* Pause Interrupt is : Disabled (0)  */
  /* End Of Queue Interrupt is : Disabled (0)  */
  /* CFIFO Underflow Interrupt is : Disabled (0)  */
  /* CFIFO Fill Enable is : Enabled (1)  */
  /* CFIFO Fill Select : Enabled (1)  */
  /* RFIFO Overflow Interrupt is : Disabled (0)  */
  /* RFIFO Drain is : Enabled (1)  */
  /* RFIFO Drain Select is : Enabled (1)  */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR0  */
  EQADC.IDCR[1].R = 0x0000;             /* NonCoherency Interrupt is : Disabled (0)  */
  /* Trigger Overrun Interrupt is :Disabled (0)  */
  /* Pause Interrupt is : Disabled (0)  */
  /* End Of Queue Interrupt is : Disabled (0)  */
  /* CFIFO Underflow Interrupt is : Disabled (0)  */
  /* CFIFO Fill Enable is : Disabled (0)  */
  /* CFIFO Fill Select : Disabled (0)  */
  /* RFIFO Overflow Interrupt is : Disabled (0)  */
  /* RFIFO Drain is : Disabled (0)  */
  /* RFIFO Drain Select is : Disabled (0)  */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR1   */
  EQADC.IDCR[2].R = 0x0000;             /* NonCoherency Interrupt is : Disabled (0)  */
  /* Trigger Overrun Interrupt is :Disabled (0)  */
  /* Pause Interrupt is : Disabled (0)  */
  /* End Of Queue Interrupt is : Disabled (0)  */
  /* CFIFO Underflow Interrupt is : Disabled (0)  */
  /* CFIFO Fill Enable is : Disabled (0)  */
  /* CFIFO Fill Select : Disabled (0)  */
  /* RFIFO Overflow Interrupt is : Disabled (0)  */
  /* RFIFO Drain is : Disabled (0)  */
  /* RFIFO Drain Select is : Disabled (0)  */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR1   */
  EQADC.IDCR[3].R = 0x0000;             /* NonCoherency Interrupt is : Disabled (0)  */
  /* Trigger Overrun Interrupt is :Disabled (0)  */
  /* Pause Interrupt is : Disabled (0)  */
  /* End Of Queue Interrupt is : Disabled (0)  */
  /* CFIFO Underflow Interrupt is : Disabled (0)  */
  /* CFIFO Fill Enable is : Disabled (0)  */
  /* CFIFO Fill Select : Disabled (0)  */
  /* RFIFO Overflow Interrupt is : Disabled (0)  */
  /* RFIFO Drain is : Disabled (0)  */
  /* RFIFO Drain Select is : Disabled (0)  */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR2   */
  EQADC.IDCR[4].R = 0x0000;             /* NonCoherency Interrupt is : Disabled (0)  */
  /* Trigger Overrun Interrupt is :Disabled (0)  */
  /* Pause Interrupt is : Disabled (0)  */
  /* End Of Queue Interrupt is : Disabled (0)  */
  /* CFIFO Underflow Interrupt is : Disabled (0)  */
  /* CFIFO Fill Enable is : Disabled (0)  */
  /* CFIFO Fill Select : Disabled (0)  */
  /* RFIFO Overflow Interrupt is : Disabled (0)  */
  /* RFIFO Drain is : Disabled (0)  */
  /* RFIFO Drain Select is : Disabled (0)  */

  /* EQADC Interrupt and DMA Control Registers (EQADC_IDCR) IDCR2   */
  EQADC.IDCR[5].R = 0x0000;             /* NonCoherency Interrupt is : Disabled (0)  */
  /* Trigger Overrun Interrupt is :Disabled (0)  */
  /* Pause Interrupt is : Disabled (0)  */
  /* End Of Queue Interrupt is : Disabled (0)  */
  /* CFIFO Underflow Interrupt is : Disabled (0)  */
  /* CFIFO Fill Enable is : Disabled (0)  */
  /* CFIFO Fill Select : Disabled (0)  */
  /* RFIFO Overflow Interrupt is : Disabled (0)  */
  /* RFIFO Drain is : Disabled (0)  */
  /* RFIFO Drain Select is : Disabled (0)  */

  /* EQADC CFIFO Control Register 0 (EQADC_CFCR0)  CFIFO-0                    */
  EQADC.CFCR[0].R = 0x0010;             /* Single Scan Enable Bit - 0            */
  /* CFIFO Invalidate Bit -0               */
  /* CFIFO Operation Mode - Software Trigger  */
  /* Trigger - Single Scan Mode  */

  /* EQADC CFIFO Control Register 0 (EQADC_CFCR0)  CFIFO-1                    */
  EQADC.CFCR[1].R = 0x0000;             /* Single Scan Enable Bit - 0             */
  /* CFIFO Invalidate Bit - 0                */
  /* CFIFO Operation Mode -  Disabled   */
  /* Trigger -  Disabled  Scan Mode  */

  /* EQADC CFIFO Control Register 1 (EQADC_CFCR1)  CFIFO-2                    */
  EQADC.CFCR[2].R = 0x0000;             /* Single Scan Enable Bit - 0             */
  /* CFIFO Invalidate Bit - 0                */
  /* CFIFO Operation Mode - 0 Disabled   */
  /* Trigger -  Disabled  Scan Mode  */

  /* EQADC CFIFO Control Register 1 (EQADC_CFCR1)   CFIFO-3                   */
  EQADC.CFCR[3].R = 0x0000;             /* Single Scan Enable Bit - 0             */
  /* CFIFO Invalidate Bit                */
  /* CFIFO Operation Mode -  Disabled   */
  /* Trigger -  Disabled  Scan Mode  */

  /* EQADC CFIFO Control Register 2 (EQADC_CFCR2)  CFIFO-4                   */
  EQADC.CFCR[4].R = 0x0000;             /* Single Scan Enable Bit - 0            */
  /* CFIFO Invalidate Bit - 0                */
  /* CFIFO Operation Mode -  Disabled   */
  /* Trigger -  Disabled  Scan Mode  */

  /* EQADC CFIFO Control Register 2  (EQADC_CFCR2)   CFIFO-5                  */
  EQADC.CFCR[5].R = 0x0000;             /* Single Scan Enable Bit - 0            */
  /* CFIFO Invalidate Bit - 0                */
  /* CFIFO Operation Mode -  Disabled   */
  /* Trigger -  Disabled  Scan Mode  */
}
/* ********************************************************************** 
 *
 *                           End of File 
 *
 * ********************************************************************* */

