/* ######################################################################  
 *                                                                            
 *                           RAppID                                          
 *     Rapid Application Initialization and Documentation Tool               
 *                     freescale Virtual Garage                              
 *                   MPC5553 Configuration Tool                             
 *          Automatically Generated Initilization Code                      
 *                                                                          
 *                                                                          
 * #######################################################################  
 *                                                                          
 *  Project Name: base   
 *                                                                          
 *  Project File: base.mat           
 *                                                                          
 *  Revision Number: 1.85   
 *                          
 *  Tool Version: 1.1.1   
 *                          
 *  Target Compiler: metrowerks   
 *                          
 *  Target Part: 5554      
 *                          
 *  Part Errata Fixes: None
 *                          
 *  Project Last Save Date: 25-Sep-2008 20:48:19   
 *                          
 *  FunctionName::dma_init::FunctionName 
 *                          
 *  Date : 25-Sep-2008  Time : 20:48:27.41
 *
 * ####################################################################### */

/* ******************  Dependent Include files Here ********************** */
#include "mpc5554.h"
#include "dma_init_hdr.h"

/* ********************* Register Macros ****************************** */

#define CFIFO0_PUSH                     0xFFF80010
#define CFIFO1_PUSH                     0xFFF80014
#define CFIFO2_PUSH                     0xFFF80018
#define CFIFO3_PUSH                     0xFFF8001C
#define CFIFO4_PUSH                     0xFFF80020
#define CFIFO5_PUSH                     0xFFF80024
/*  The POP Register Adresses are for the lower 16 Bits Since the lower word contains the result data */
/*  The Upper 16 Bits read as 0000 and do not contain any data                                        */
#define RFIFO0_POP                      0xFFF80032
#define RFIFO1_POP                      0xFFF80036
#define RFIFO2_POP                      0xFFF8003A
#define RFIFO3_POP                      0xFFF8003E
#define RFIFO4_POP                      0xFFF80042
#define RFIFO5_POP                      0xFFF80046
#define DSPI_B_PUSH                     0xFFF94034
#define DSPI_C_PUSH                     0xFFF98034
#define DSPI_D_PUSH                     0xFFF9C034
/*  The POP Register Adresses are for the lower 16 Bits Since the lower word contains the result data */
/*  The Upper 16 Bits read as 0000 and do not contain any data                                        */
#define DSPI_B_POP                      0xFFF9403A
#define DSPI_C_POP                      0xFFF9803A
#define DSPI_D_POP                      0xFFF9C03A

/* ********************* Pragma Section ********************* */

/* ******************* Externally Referenced Variables ******************* */

extern vuint32_t CQUEUE0[1];            /* CFIFO 0 Queue Variable declaration */

extern vuint16_t RQUEUE0[1];            /* RFIFO 0 Queue Variable declaration */

/* ********************* Initilization Function ********************* */
void dma_int_fcn_NameX(void)
{
  /* DMA Configuration Register (DMACR)                     */
  EDMA.CR.R = 0x00000400;               /* Group Arbitration scheme is : Fixed Priority  */
  /* Channel Arbitration Scheem is : Fixed Priority  */
  /* Group 1 Priority (GRP1PRI) is : 1 */
  /* Group 0 Priority (GRP0PRI) is : 0 */
  /* Debug is : Disabled (0) */

  /* DMA Enable Error Interrupt Request Registers (DMAEEIL)                      */
  EDMA.EEIRL.R = 0x00000000;            /* DMA Error Interrupt Enable Register Low (Channels 0-31) :  */

  /* DMA Channel Priority Register Settings (DCHPRIn) Channels 0 - 31                    */
  EDMA.CPR[0].R = 0x00;                 /* Channel 0 is Priority 1, Channel Preemption is Disabled */
  EDMA.CPR[1].R = 0x01;                 /* Channel 1 is Priority 2, Channel Preemption is Disabled */
  EDMA.CPR[2].R = 0x02;                 /* Channel 2 is Priority 3, Channel Preemption is Disabled */
  EDMA.CPR[3].R = 0x03;                 /* Channel 3 is Priority 4, Channel Preemption is Disabled */
  EDMA.CPR[4].R = 0x04;                 /* Channel 4 is Priority 5, Channel Preemption is Disabled */
  EDMA.CPR[5].R = 0x05;                 /* Channel 5 is Priority 6, Channel Preemption is Disabled */
  EDMA.CPR[6].R = 0x06;                 /* Channel 6 is Priority 7, Channel Preemption is Disabled */
  EDMA.CPR[7].R = 0x07;                 /* Channel 7 is Priority 8, Channel Preemption is Disabled */
  EDMA.CPR[8].R = 0x08;                 /* Channel 8 is Priority 9, Channel Preemption is Disabled */
  EDMA.CPR[9].R = 0x09;                 /* Channel 9 is Priority 10, Channel Preemption is Disabled */
  EDMA.CPR[10].R = 0x0A;                /* Channel 10 is Priority 11, Channel Preemption is Disabled */
  EDMA.CPR[11].R = 0x0B;                /* Channel 11 is Priority 12, Channel Preemption is Disabled */
  EDMA.CPR[12].R = 0x0C;                /* Channel 12 is Priority 13, Channel Preemption is Disabled */
  EDMA.CPR[13].R = 0x0D;                /* Channel 13 is Priority 14, Channel Preemption is Disabled */
  EDMA.CPR[14].R = 0x0E;                /* Channel 14 is Priority 15, Channel Preemption is Disabled */
  EDMA.CPR[15].R = 0x0F;                /* Channel 15 is Priority 16, Channel Preemption is Disabled */
  EDMA.CPR[16].R = 0x00;                /* Channel 16 is Priority 1, Channel Preemption is Disabled */
  EDMA.CPR[17].R = 0x01;                /* Channel 17 is Priority 2, Channel Preemption is Disabled */
  EDMA.CPR[18].R = 0x82;                /* Channel 18 is Priority 3, Channel Preemption is Enabled */
  EDMA.CPR[19].R = 0x03;                /* Channel 19 is Priority 4, Channel Preemption is Disabled */
  EDMA.CPR[20].R = 0x04;                /* Channel 20 is Priority 5, Channel Preemption is Disabled */
  EDMA.CPR[21].R = 0x05;                /* Channel 21 is Priority 6, Channel Preemption is Disabled */
  EDMA.CPR[22].R = 0x06;                /* Channel 22 is Priority 7, Channel Preemption is Disabled */
  EDMA.CPR[23].R = 0x07;                /* Channel 23 is Priority 8, Channel Preemption is Disabled */
  EDMA.CPR[24].R = 0x08;                /* Channel 24 is Priority 9, Channel Preemption is Disabled */
  EDMA.CPR[25].R = 0x09;                /* Channel 25 is Priority 10, Channel Preemption is Disabled */
  EDMA.CPR[26].R = 0x0A;                /* Channel 26 is Priority 11, Channel Preemption is Disabled */
  EDMA.CPR[27].R = 0x0B;                /* Channel 27 is Priority 12, Channel Preemption is Disabled */
  EDMA.CPR[28].R = 0x0C;                /* Channel 28 is Priority 13, Channel Preemption is Disabled */
  EDMA.CPR[29].R = 0x0D;                /* Channel 29 is Priority 14, Channel Preemption is Disabled */
  EDMA.CPR[30].R = 0x0E;                /* Channel 30 is Priority 15, Channel Preemption is Disabled */
  EDMA.CPR[31].R = 0x0F;                /* Channel 31 is Priority 16, Channel Preemption is Disabled */

  /*  Transfer Control Descriptor's for the EQADC DMA Interface.    */
  /*  Transfer Control Descriptor for CFIFO 00 - CH0  */
  EDMA.TCD[0].SADDR = (vuint32_t) &CQUEUE0; /*  Start Address  */
  EDMA.TCD[0].DADDR = CFIFO0_PUSH;      /*  Destination address */
  EDMA.TCD[0].SMOD = 0x00;              /*  Source address modulo  */
  EDMA.TCD[0].DMOD = 0x00;              /*  Destination address modulo  */
  EDMA.TCD[0].DSIZE = 0x02;             /*  Destination transfer size : 32 Bits  */
  EDMA.TCD[0].SSIZE = 0x02;             /*  Source transfer size : 32 Bits  */
  EDMA.TCD[0].SOFF = (vint16_t)0x4;     /*  Signed source address offset */
  EDMA.TCD[0].NBYTES = 0x00000004;      /*  Inner "minor" byte count  */
  EDMA.TCD[0].SLAST = (vint32_t)0xFFFFFFFC; /*  last Signed source address adjust */
  EDMA.TCD[0].DOFF = (vint16_t)0x0;     /*  Signed destination address offset */
  EDMA.TCD[0].DLAST_SGA = (vint32_t)0x0; /*  Signed destination address adjust */
  EDMA.TCD[0].BITERE_LINK = 0x00;       /*  Disable Channel Linking  Minor Loop Channel Linking Disabled*/
  EDMA.TCD[0].BITER=0x0001;             /*  Beginning "major" iteration count - Minor Loop Channel Linking Disabled*/
  EDMA.TCD[0].CITERE_LINK = 0x00;       /*  Disable Channel Linking  Minor Loop Channel Linking Disabled*/
  EDMA.TCD[0].CITER=0x0001;             /*  Current "major" iteration count - Minor Loop Channel Linking Disabled*/
  EDMA.TCD[0].BWC = 0x00;               /*  Bandwidth control :  No DMA Stalls  */
  EDMA.TCD[0].MAJORLINKCH = 0x00;       /*  Major Channel number */
  EDMA.TCD[0].MAJORE_LINK = 0x0;        /*  Major Channel Link : Disabled */
  EDMA.TCD[0].DONE = 0x00;              /*  Channel Done  */
  EDMA.TCD[0].ACTIVE = 0x00;            /*  Channel ACtive  */
  EDMA.TCD[0].E_SG = 0x0;               /*  Enable Scatter/Gather : Disabled */
  EDMA.TCD[0].D_REQ = 0x0;              /*  Disables the DMA Channel when done  */
  EDMA.TCD[0].INT_HALF = 0x0;           /*  Interrupt on minor loop count : Disabled */
  EDMA.TCD[0].INT_MAJ = 0x0;            /*  Interrupt on major loop completion : Disabled */
  EDMA.TCD[0].START = 0x00;             /*  Explicit Channel Start bit */

  /*  Transfer Control Descriptor for RFIFO 00 - CH1  */
  EDMA.TCD[1].SADDR = RFIFO0_POP;       /*  Start Address  */
  EDMA.TCD[1].DADDR = (vuint32_t) &RQUEUE0; /*  Destination address */
  EDMA.TCD[1].SMOD = 0x00;              /*  Source address modulo  */
  EDMA.TCD[1].DMOD = 0x00;              /*  Destination address modulo  */
  EDMA.TCD[1].DSIZE = 0x01;             /*  Destination transfer size : 16 Bits  */
  EDMA.TCD[1].SSIZE = 0x01;             /*  Source transfer size : 16 Bits  */
  EDMA.TCD[1].SOFF = (vint16_t)0x0;     /*  Signed source address offset */
  EDMA.TCD[1].NBYTES = 0x00000002;      /*  Inner "minor" byte count  */
  EDMA.TCD[1].SLAST = (vint32_t)0x0;    /*  Last Signed source address adjust */
  EDMA.TCD[1].DOFF = (vint16_t)0x2;     /*  Signed destination address offset */
  EDMA.TCD[1].DLAST_SGA = (vint32_t)0xFFFFFFFE; /*  Signed destination address adjust  */
  EDMA.TCD[1].BITERE_LINK = 0x00;       /*  Disable Channel Linking  Minor Loop Channel Linking Disabled*/
  EDMA.TCD[1].BITER=0x0001;             /*  Beginning "major" iteration count - Minor Loop Channel Linking Disabled*/
  EDMA.TCD[1].CITERE_LINK = 0x00;       /*  Disable Channel Linking  Minor Loop Channel Linking Disabled*/
  EDMA.TCD[1].CITER=0x0001;             /*  Current "major" iteration count - Minor Loop Channel Linking Disabled*/
  EDMA.TCD[1].BWC = 0x00;               /*  Bandwidth control :  No DMA Stalls  */
  EDMA.TCD[1].MAJORLINKCH = 0x00;       /*  Major Channel number */
  EDMA.TCD[1].MAJORE_LINK = 0x0;        /*  Major Channel Link : Disabled */
  EDMA.TCD[1].DONE = 0x00;              /*  Channel Done  */
  EDMA.TCD[1].ACTIVE = 0x00;            /*  Channel ACtive  */
  EDMA.TCD[1].E_SG = 0x0;               /*  Enable Scatter/Gather : Disabled */
  EDMA.TCD[1].D_REQ = 0x0;              /*  Disables the DMA Channel when done  */
  EDMA.TCD[1].INT_HALF = 0x0;           /*  Interrupt on minor loop count : Disabled */
  EDMA.TCD[1].INT_MAJ = 0x0;            /*  Interrupt on major loop completion : Disabled */
  EDMA.TCD[1].START = 0x00;             /*  Explicit Channel Start bit */

  /*  Transfer Control Descriptor's for the DSPI DMA Interface.    */
  /*  Transfer Control Descriptor's for the EMIOS DMA Interface.    */
  /*  Transfer Control Descriptor's for the SCI DMA Interface.    */
  /*  Transfer Control Descriptor for SCI A TX FIFO  - CH18  */
  EDMA.TCD[18].SADDR = 0x00000000;      /*  Start Address  */
  EDMA.TCD[18].DADDR = 0xFFFB0006;      /*  Destination address */
  EDMA.TCD[18].SMOD = 0x00;             /*  Source address modulo  */
  EDMA.TCD[18].DMOD = 0x00;             /*  Destination address modulo  */
  EDMA.TCD[18].DSIZE = 0x00;            /*  Destination transfer size :  8 Bits  */
  EDMA.TCD[18].SSIZE = 0x00;            /*  Source transfer size :  8 Bits  */
  EDMA.TCD[18].SOFF = (vint16_t)0x1;    /*  Signed source address offset */
  EDMA.TCD[18].NBYTES = 0x00000001;     /*  Inner "minor" byte count  */
  EDMA.TCD[18].SLAST = (vint32_t)0xFFFFFFF4; /*  last Signed source address adjust */
  EDMA.TCD[18].DOFF = (vint16_t)0x0;    /*  Signed destination address offset */
  EDMA.TCD[18].DLAST_SGA = (vint32_t)0x0; /*  Signed destination address adjust */
  EDMA.TCD[18].BITERE_LINK = 0x00;      /*  Disable Channel Linking  Minor Loop Channel Linking Disabled*/
  EDMA.TCD[18].BITER=0x0001;            /*  Beginning "major" iteration count - Minor Loop Channel Linking Disabled*/
  EDMA.TCD[18].CITERE_LINK = 0x00;      /*  Disable Channel Linking  Minor Loop Channel Linking Disabled*/
  EDMA.TCD[18].CITER=0x0001;            /*  Current "major" iteration count - Minor Loop Channel Linking Disabled*/
  EDMA.TCD[18].BWC = 0x00;              /*  Bandwidth control :  No DMA Stalls  */
  EDMA.TCD[18].MAJORLINKCH = 0x00;      /*  Major Channel number */
  EDMA.TCD[18].MAJORE_LINK = 0x0;       /*  Major Channel Link : Disabled */
  EDMA.TCD[18].DONE = 0x00;             /*  Channel Done  */
  EDMA.TCD[18].ACTIVE = 0x00;           /*  Channel ACtive  */
  EDMA.TCD[18].E_SG = 0x0;              /*  Enable Scatter/Gather : Disabled */
  EDMA.TCD[18].D_REQ = 0x0;             /*  Disables the DMA Channel when done  */
  EDMA.TCD[18].INT_HALF = 0x0;          /*  Interrupt on minor loop count : Disabled */
  EDMA.TCD[18].INT_MAJ = 0x1;           /*  Interrupt on major loop completion : Enabled */
  EDMA.TCD[18].START = 0x00;            /*  Explicit Channel Start bit */

  /*  Transfer Control Descriptor's for the ETPU DMA Interface.    */
  /* DMA Enable Request Registers (DMAERQL)                     */
  EDMA.ERQRL.R = 0x00000003;            /* DMA Enable Request Register Low (Channels 0-31) */
}
/* ********************************************************************** 
 *
 *                           End of File 
 *
 * ********************************************************************* */

