EECS 470: Computer Architecture

An advanced course on computer architecture. Design a fully synthesizable, out-of-order processor.

Syllabus

This Week

All times are listed as Ann Arbor local time (ET)

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People

Reach us at eecs470staff@umich.edu

Assignments

Textbook

Schedule

Day	Lecture Topic	Lab Topic	Deadline	Reading
Week 1Thu 1/5	Class intro
Fri 1/06		Tools Tutorial
Week 2Tue 1/10	Performance, Power, ISA			1,A
Thu 1/12	Pipelining & Hazards I			C.1-C.4
Fri 1/13		Build System	HW 1
Week 3Tue 1/17	Pipelining & Hazards II		P1 (Tue 1/17)	C.5-C.7,3.1-3.3,3.10
Thu 1/19	Scoreboard Scheduling			C.5-C.7,3.1-3.3,3.10
Fri 1/20		Debugging FSMs
Week 4Tue 1/24	Tomasulo Scheduling		P2 (Mon 1/23)	3.4-3.6
Thu 1/26	Precise Interrupts			3.8-3.9, 3.13
Fri 1/27		Git + More Testbenches	HW 2
Week 5Tue 1/31	P6 Case Study		P3 Checkpoint (Tue 1/31)
Thu 2/2	MIPS R10K Case Study			3.11
Fri 2/3		Writing Scripts
Week 6Tue 2/7	Memory Disambiguation
Thu 2/9	Instruction Flow			3.3, 3.9
Fri 2/10		SystemVerilog	P3
Week 7Tue 2/14	[No lecture]		Project Proposal
Thu 2/16	Midterm Review
Fri 2/17		[No lab]	HW 3
Week 8Tue 2/21	Midterm (7-9 pm)
Thu 2/23	Wide Instruction Flow			3.3, 3.9
Fri 2/24		[No lab]
Week 9Tue 2/28	Spring Break
Tue 3/2	Spring Break
Fri 3/3	Spring Break	[No lab]
Week 10Tue 3/7	Caches I		Milestone 1	2.1
Thu 3/9	Caches II
Fri 3/10		[No lab]
Week 11Tue 3/14	Prefetching
Thu 3/16	Virtual Memory
Fri 3/17		Memory Lab	HW 4
Week 12Tue 3/21	Multiprocessors I
Thu 3/23	Guest Lecture: Joshua Smith		Milestone 2
Fri 3/24		[No lab]
Week 13Tue 3/28	Multiprocessors I
Thu 3/30	Simultaneous Multithreading
Fri 3/31		[No lab]
Week 14Tue 4/4	Data Level Parallelism
Thu 4/6	TBA		Milestone 3
Fri 4/7		[No lab]
Week 15Tue 4/11	TBA
Thu 4/13	TBA
Fri 4/14		[No lab]	Final Project Due
Week 16Tue 4/18	Project Presentations		HW 5
Week 17Tue 4/27	Final Exam 8:00 AM - 10:00 AM