< EECS 470 Winter 2019
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Course Info

LecturesTues. & Thu. 12:00 - 1:20 PM in 1670 BBB
LabsThu 4:00-6:00 PM; 1620 BBB Fri 10:00 AM -12:00 PM; 1620 BBB
MidtermTBD
Final ExamThu May 2, 1:30-3:30 PM, TBD
Web Pagehttp://www.eecs.umich.edu/courses/eecs470/
Canvashttp://umich.instructure.com/courses/233463
Lecture Recordingshttps://leccap.engin.umich.edu/leccap/site/0zyeyah1k2hey264x1
InstructorRon Dreslinski
Emailrdreslin /at/ umich.edu
Office HoursTuesday 4:30-6:30pm 2637 BBB, Thursday 1:30-:230pm 2637 BBB
GSIJames Connolly
Emailconjam /at/ umich.edu
Office HoursTuesday 2:30pm-4:30pm 1620 BBB, Wednesday 5-7pm 1620 BBB
GSIJielun Tan
Emailjieltan /at/ umich.edu
Office HoursMonday 12pm-2pm 1620 BBB, Wednesday 3-5pm 1620 BBB
IAYichen Yang
Emailyangych /at/ umich.edu
Office HoursSunday 3-5p 1620 BBB

Description

What is computer architecture?

Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course qualitatively and quantitatively examines computer design trade-offs. We will learn, for example, how uniprocessors execute many instructions concurrently and why state-of-the-art memory systems are nearly as complex as processors.

EECS 470 is an advanced undergraduate/introductory graduate-level course in computer architecture. This course is intended to do two things: to give you a solid, detailed understanding of how computers are designed and implemented, including the central processor, memory and I/O interfaces; and to make you aware of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems. We will cover pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), I/O interfaces, operating system issues, and basic multiprocessor systems.

A central part of EECS 470 is the detailed design of major portions of a substantial processor using the SystemVerilog hardware design language (HDL), IEEE 1800-2017. Portions of this work will be done individually as homeworks; the bulk of the work will be done in groups of three to five as a term project during the last 9 or 10 weeks of the semester. You will use modern commercial CAD tools to develop your design. This project represents a significant investment of time on your part, and is a significant portion of your grade in this class. However, in computer architecture it is particularly true that "the devil is in the details," and you will gain important experience and knowledge by coming face to face with that devil.

What knowledge does EECS 470 assume?

EECS 470 assumes that you are familiar with the following material: