< EECS 470 Fall 2017
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Introduction
(1)   H&P Chapter 1 (5th edition)
Performance, Power, and Instruction Set Architectures
(1)   H&P Chapter 1, Appendix A
Pipelining & Hazards I
(1)   H&P Appendix C.1-C.4
Pipelining & Hazards II
Scoreboard Scheduling
(1)   H&P Appendix C.5-C.7, Chapter 3.1-3.3,3.10
Tomasulo Scheduling
(1)   H&P Chapter 3.4-3.6
PDF (2)   D. Sima, The Design Space of Register Renaming Techniques, IEEE Micro, Sep./Oct. 2000.
Precise Interrupts
(1)   H&P Chapter 3.8-3.9
PDF (2)   J. Smith, A. Pleszkun, Implementing Precise Interrupts, Proceedings of the 12th International Symposium on Computer Architecture, June 1985.
P6 Microarchitectures
(1)   H&P Chapter 3.13
MIPS R10K Microarchitectures
PDF (1)   K. C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, V. 16, No. 2, Apr. 1996.
Memory Speculation
(1)   H&P Chapter 3.11
Instruction Flow
(1)   H&P Chapter 3.3
Wide Instruction Flow
PDF (1)   S. McFarling, Combining Branch Predictors, WRL Technical Note TN-36, June 1993.
(2)   H&P Chapter 3.9
Basic Caches
(1)   H&P Chapter 2.1
Lowering Miss Rate
(1)   H&P Chapter 2.2,2.3,B.3
Prefetching
(1)   B. Falsafi & T. F. Wenisch, A Primer on Hardware Prefetching.
Virtual Memory
(1)   H&P Chapter 2.4,B.4,B.5
DRAM & Storage
(1)   H&P Chapter D
Multiprocessors
(1)   H&P Chapter 5.2,5.3
Data Centers
(1)   H&P Chapter 6
Supplemental Material
(1)   International Technology Roadmap for Semiconductors, 2005 Edition, Executive Summary.