< EECS 470 Fall 2017

EECS 470 Computer Architecture

Fall 2016

Course Info

LecturesMon. & Wed. 3:10 - 4:30 PM in 1303 EECS
LabsFri 10:00-12:00 PM; 1620 BBB and Fri. 12:30 AM - 2:30 PM; 1620 BBB
MidtermTBD, Perhaps Evening of October 19
Final ExamMon December 18, 4:00-6:00 PM
Web Pagehttp://www.eecs.umich.edu/courses/eecs470/
InstructorRon Dreslinski
Emailrdreslin /at/ umich.edu
Office2637 BBB
Office HoursM 4:30-6, Tu 2-3
IAJielun Tan
Emailjieltan /at/ umich.edu
Office HoursSu 12-1:30 1620 Beyster, Th 6-8:00 1620 Beyster
IAThomas Rupp
Emailtmrupp /at/ umich.edu
Office HoursM 4:30-6:30 1695 Beyster, Tu 12:30-2:30 1620 Beyster
GSISteve Zekany
Emailszekany /at/ umich.edu
Office HoursM 10-11:30am 1695 Beyster, W 4:30-6:00 1695 Beyster


Optional Text   Computer Architecture: A Quantitative Approach (Fifth Edition)
by John L. Hennessy and David A. Patterson
published by Morgan-Kaufmann publishers.
Electronic copy available via link at left.
Technical Papers   Listed on class schedule web page
Reading Guidelines   Alan Jay Smith, The Task of the Referee, IEEE Computer, Apr. 1990
Talk Guidelines   Mark Hill, Oral Presentation Advice
On-line Publications   ACM Proceedings Online
IEEE Proceedings Online


You are responsible for all the material covered in class including handouts and class notes. Attendance at the discussion section is mandatory and very very useful. The GSIs will present vital information on the Verilog language, the basic pipeline design you will be extending, and the CAD tools you will be using. Do not register for this course unless you can attend the discussion section. If you are unable to appear for an exam for any reason, you must contact Prof. Wenisch before the exam.


What is computer architecture?

Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course qualitatively and quantitatively examines computer design trade-offs. We will learn, for example, how uniprocessors execute many instructions concurrently and why state-of-the-art memory systems are nearly as complex as processors.

EECS 470 is an advanced undergraduate/introductory graduate-level course in computer architecture. This course is intended to do two things: to give you a solid, detailed understanding of how computers are designed and implemented, including the central processor, memory and I/O interfaces; and to make you aware of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems. We will cover pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), I/O interfaces, operating system issues, and basic multiprocessor systems.

A central part of EECS 470 is the detailed design of major portions of a substantial processor using the Verilog hardware design language (HDL). Portions of this work will be done individually as homeworks; the bulk of the work will be done in groups of three to five as a term project. You will use modern commercial CAD tools to develop your design. This project represents a significant investment of time on your part, and is a significant portion of your grade in this class. However, in computer architecture it is particularly true that "the devil is in the details," and you will gain important experience and knowledge by coming face to face with that devil.

What knowledge does EECS 470 assume?

EECS 470 assumes that you are familiar with the following material:
  • Basic digital logic design (EECS 270 or equivalent)
  • Basic machine organization (EECS 370 or equivalent)
  • Assembly language programming: opcodes, operands, etc.
  • High-level languages and data structures
  • Verilog hardware description (covered in discussion, but prior experience is helpful)


All assignments will be available on the course home page. Your solutions to the assigned problems are due at the beginning of the class period on the specified due date, and will be submitted via GradeScope. Prof. Wenisch does not accept late homework.


A tentative breakdown of grade is given below.
Homework   9%
Programming Projects   7%
Lab Assignments   1%
Midterm   24%
Final   24%
Project   35%
Participation & Discussion   Counts
There will be 5 or 6 homework assignments. The lowest homework grade will be dropped.

You must achieve passing grades on the both the project/homework as well as on the exams in order to pass the class! A rough measure of passing is that those within 1.75 standard deviations of the median of the students receiving a grade would be considered passing. A passing grade is a "C".

Academic Honesty

You are encouraged to interact with other students to discuss course material, form study groups for the exams, help each other learn Verilog and the CAD tools, and provide each other with debugging assistance, encouragement, and moral support. However, all individual assignments (i.e., homeworks and exams) are to be performed on your own (i.e., copying off someone else is prohibited), and all group assignments (i.e., the project) are to be performed only by members of the group.

Referring to homeworks or projects from previous semesters is strictly forbidden.

The Engineering Honor Code obligates you not only to abide by this policy, but also to report any violations that you become aware of. Violations of this policy will be brought to the College of Engineering's Honor Council. For more information on the Honor Code, see Honor Council web page. If you have any doubts about whether a certain level of collaboration is permissible, or any other questions, contact the professor.