EECS 470: Computer Architecture

Winter 2012

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Overview

There will be ~6 homework assignments, ~5 (short) inlab assignments, 3 Verilog programming assignments, and 1 class project. The approximate due dates for all of this can be found on the class schedule.

Changes to due dates in class schedule:

Homework

Homework is due at the start of class (or if due in lab/discussion the start of lab).

Verilog

Verilog handouts

In lab

Lab Checkoffs: (Google Docs)

Verilog Programming Projects


Home / announcements | Course overview | Staff and hours
References / Notes / Handouts | Homework/Projects | Exams