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There will be ~6 homework assignments, ~5 (short) inlab assignments, 3 Verilog programming assignments, and 1 class project. The approximate due dates for all of this can be found on the class schedule.Changes to due dates in class schedule:
- None at this time.
Homework is due at the start of class (or if due in lab/discussion the start of lab).
- Homework 1 (ans)
- Homework 2 (ans)
- Homework 3 (ans)
- Homework 4 (ans)
- Homework 5 (ans)
Verilog handouts
These handouts are fairly old, but darn useful...
- Verilog overview for EECS 470.
- 15 points to follow while writing Verilog
- Synthesis and Makefile overview
In lab
Lab Checkoffs: (Google Docs)
- Inlab 1
- Inlab 2
- Inlab 3
- Inlab 4
- Inlab 5
- Slides from Lab
- Tarball (Assignment in tarball)
- Inlab 6
Verilog Programming Projects
- Assignment #1 and its tarball P1.tar.gz.
- Assignment #2 and its tarball P2.tar.gz
- Assignment #3 (ignore the part about it being a day later than the course schedule) and its tarball P3.tar.gz
- The Alpha 64 subset for 470 (Old version)
- Alpha assembly language guide
- Alpha architecture handbook - pdf describing the Alpha instructions
- Example output
Final Project
- Project assignment
- Skeleton Tarball
- Changes to build system / Makefile (Phorum)
- Some Sample Verilog Modules...
- prime.s, an additional test case.
- mult_no_lsq.s, very useful test case for everything non-memory related.
- Final Project Advice
- Final Project Hand-in
- decaf470.tar.gz--This is a student independent study project that you might find useful for generating additional test cases. We provide no warranty, no support and our best wishes.
| Home / announcements | Course overview | Staff and hours |
| References / Notes / Handouts | Homework/Projects | Exams |