Full syllabus: pdfAlternate Exam Request: Google Form
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The following schedule may change for all sorts of reasons. Nothing here should be taken as for certain, and we likely will not be updating it as the semester goes forward...
- Class schedule (pdf).
Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course qualitatively and quantitatively examines computer design trade-offs. We will learn, for example, how uniprocessors execute many instructions concurrently and why state-of-the-art memory systems are nearly as complex as processors.
EECS 470 is an advanced undergraduate/introductory graduate-level course in computer architecture. This course is intended to do two things: to give you a solid, detailed understanding of how computers are designed and implemented, including the central processor and memory; and to make you aware of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems. We will cover pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), operating system issues, and basic multiprocessor systems.
A central part of EECS 470 is the detailed design of major portions of a substantial processor using the Verilog hardware design language (HDL). Portions of this work will be done individually as homeworks; the bulk of the work will be done in groups of five to six as a term project. You will learn to use modern commercial CAD tools to develop your design. This project represents a significant investment of time on your part, and is a significant portion of your grade in this class. However, in computer architecture it is particularly true that "the devil is in the details," and you will gain important experience and knowledge by coming face to face with that devil.
Upon satisfactory completion of this course, you will be able to describe and model the detailed mechanics of modern microarchitectures. You will be able to implement arbitrary hardware specifications using industry standard tools and have several concrete strategies for verifying them. You will be well equipped to begin reading publications in top-tier computer architecture conferences and make substantive critiques.
EECS 470 assumes that you are familiar with the following material:
- Basic digital logic design (EECS 270 or equivalent)
- Basic machine organization (EECS 370 or equivalent)
- Assembly language programming: opcodes, operands, etc.
- High-level languages and data structures
- Verilog hardware description (covered in discussion, but prior experience is helpful)
Computer Architecture: A Quantitative Approach, 5th or 6th edition, by Hennessy and Patterson, Morgan Kaufman Publishers.
An on-line copy of the book is available for the 5th edition.Recommended reference (optional): Verilog Styles for Synthesis of Digital Systems, 1st edition, by Smith and Franzon, Prentice Hall.
- Attendance at the lab section is mandatory and very very useful. The GSIs will present vital information on the Verilog language, the basic pipeline design you will be extending, and the CAD tools you will be using. Do not register for this course unless you can attend the lab section.
- This course is a lot of work. You will spend many long nights debugging your processor at the end of the term. If you are registered for other classes that may interfere with your ability to dedicate a lot of time to this course, especially in the last few weeks, you should reconsider your schedule.
- For the homework and midterm you will have about 7 days to file any regrade requests. Regrade requests can result in a lower score. For the final exam, you can expect to have about 12-24 hours to file any regrade request.
- You are encouraged to interact with other students to discuss course material, form study groups for the exams, help each other learn Verilog and the CAD tools, and provide each other with debugging assistance, encouragement, and moral support. However, all individual assignments (i.e., homeworks and exams) are to be performed on your own, and all group assignments (i.e., the project) are to be performed only by members of the group.
Referring to homeworks or projects from previous semesters is strictly forbidden.
The Engineering Honor Code obligates you not only to abide by this policy, but also to report any violations that you become aware of. Violations of this policy will be brought to the College of Engineering's Honor Council. For more information on the Honor Code, see the Honor Council web page. If you have any doubts about whether a certain level of collaboration is permissible, or have any other questions, contact the professor.
Grade Distribution Homework* 10% Lab assignments 5% Project 1 2% Project 2 3% Project 3 5% Final Project 35% Exam 1 20% Exam 2 20% * There will be 5 homework assignments of equal weight. Your lowest score will be dropped.