EECS 470: Computer Architecture

Overview

There will be 5 homework assignments, 3 Verilog programming assignments, and one class project. The approximate due dates for all of this can be found on the class schedule.

Changes to due dates in class schedule:

• None at this time.

Verilog handouts

• Tools Tutorial and its tarball 470tut.tar.gz
• Verilog overview for EECS 470.
  • tbp1.v
  • tbp2.v
  • tbp_tb.v
• 15 points to follow while writing verilog
• Synthesis and Makefile overview

Verilog slides from discussion

• Discussion #1: Introduction to Verilog
• Discussion #2: Synthesis and Project 2
• Discussion #3: Makefiles and Alpha ISA
• Discussion #4: Verisimple Pipeline and Project 3
• Discussion #5: Final Project and Advanced Topics
• Discussion #6: Proposal Meetings
• Discussion #7: Final Project Common Problems
• Discussion #8: Milestone 1 Meetings
• Discussion #9: Memory and Icache Controller
• Discussion #10: Generate Statements and Prefetching

Verilog Programming Projects

• Assignment #1 and its tarball P1.tar.gz.

• Assignment #2 and its tarball P2F09.tar.gz
  Handin directions

• Assignment #3 and its tarball vsimp4_f09.tar.gz.
  • The Alpha 64 subset for 470 (Old version)
  • Alpha assembly language guide
  • Alpha architecture handbook - pdf describing the Alpha instructions
  • Example output
  • Visual Debugger guide

Homework

Homework can be handed in during class OR put in the EECS 470 box. The box is on the 2nd floor of EECS next to the men's bathroom and across from EECS 2336 (The 215 lab). It is a large wooden box on the floor labeled "EECS 470".

• Homework assignment #1
  • Figure A5 from the text
  • Answers -- Minor fixes made Oct 1st (in red)
• Homework assignment #2
  • Answers
• Homework assignment #3
  • Answers
• Homework assignment #4
  • Answers

Project info

• 470 Class project
• A sample reservation station
• Tips for the final project from Doug et al.
• WOR Example
• Copying Example - Usefule for RAT/RRAT/BRAT
• Parameterized cache
• Parameterized encoder
• Parameterized priority selector
• Mult.s without loads or stores
• Information and examples about creating multi-port memories in verilog
• Guideline to reports for the final project. Oral and written.
• In-order pipeline w/caches
• Diagram of Icache and memory interaction
• 470 Simulator for generating program outputs