We simply want to know what you did. Everything from how big your ROB is to how your memory system works. Specifically be sure to address how you met the project requirements and clearly cover aall advanced features. Provide a block-diagram of your major units with their (top-level) Verilog module names shown.
Let us know what you think works and what doesn't work for each major component. (If everything works this is going to be very short!) Be clear on what it is about that component that doesn't work. Is it perfect other than not being able to synthesize? Does it work unless a certain situation occurs? If you wrote and tested some things (e.g. better cache, better predictor) but didn't include in in the final project, tell us about it here and explain why it's not included.
We want to know who was responsible for which components. If it was more than one person, give us an idea how much each person contributed. In addition let us know who did most of the testing, design, and other high-level tasks. Finally, tell us what percent of the total effort was contributed by each person. If you don't agree with the % effort presented in the report, or your group cannot agree upon the effort put in by each person, send an e-mail to the instructors which includes in the subject the phrase "Group effort, Group X" (where X is your group number) and tell us your thoughts on the group effort. Such e-mails must be sent within 24 hours after the report deadline. This can be stressful. If you all find it annoying or stessful it's fine to just have the report indicate you'll have each person reach out individually. But take a shot at it please.
As a portion of the project you are to consider the impact of certain architectural changes. Some obvious things are to discover the impact of prefetching, cache associativity, or perhaps the impact of the size of the RS, ROB, cache, or something else. This is a good place to discuss features you tried but actually hurt performance. Clearly labeled and explained graphs are likely to be useful here. You should include things that:Please do NOT provide data on the performance of the really short "correctness" tests (halt, btestX, etc.). Please _do_ include IPC numbers of the longer tests. Also include IPC numbers for your tests you wrote as part of HW4. Include your clock perod.
- Helped you make decisions about your design
- Are interesting or non-intuitive. Things where your instructors guessed wrong are interesting.
- How well your primary advanced features work. Turn them off where you can.
You should have slides and should have practiced the presentation at least once. Each person must talk during the presentation and while the split between members talking doesn't have to be equal, it should be close.
The important things are that you let us know: