EECS 470 reports


Due date

Oral reports

We want to know:
  1. What exactly you did (or tried to do!)
  2. What works, what doesn't
  3. Who did what.
  4. Thoughts on what you did right and wrong (and even what we did right and wrong)
  5. You analysis of your advanced features.
You should have a short powerpoint presentation to class. Please bring your presentation on a USB key, or, if you prefer, bring your own laptop. You should plan on having 12-15 minutes to talk.

Written report

Remember the documentation is 10% of your grade, and analysis is 7%! Your written report should include: Your report does not need to follow a particular format (such as this outline) but be sure you address all of these issues. Your report can touch on other issues as you see fit. I'd prefer not to see reports over significantly over 10 pages unless that's needed to display data in an appendix.

What you did

We simply want to know what you did. Everything from how big your ROB is to how you did caching (sizes here too). Specifically be sure to address how you met the project requirements and any advanced features. Provide a block-diagram of your major units with their Verilog module names shown.

What works, what doesn't

Let us know what you think works and what doesn't work for each major component. (If everything works this is going to be very short!) Be clear on what it is about that component that doesn't work. Is it perfect other than not being able to synthesize? Does it work unless a certain situation occurs?

Who did what

We want to know who was responsible for which components. If it was more than one person, give us an idea how much each person contributed. In addition let us know who did most of the testing, design, and other high-level tasks. Finally, in the written report only, tell us what percent of the total effort was contributed by each person. If you don't agree with the % effort presented in the report, or your group cannot agree upon the effort put in by each person, send an e-mail to the instructors which includes in the subject the phrase "Group effort" and tell me your thoughts on the group effort. Such e-mails must be sent by Thursday the 17th by 6pm.

Analysis

As a portion of the project you are to consider the impact of certain architectural changes. Some obvious things are to discover the impact of prefetching, cache associativity, or perhaps the impact of the size of the RS, ROB, cache, or something else. This is a good place to discuss features you tried but actually hurt performance. Clearly labeled and explained graphs are likely to be useful here. This section will likely be around 2-4 pages in length.