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| Sep 9th | Course Overview |
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Read: The Future of Microprocessors Skim: The Landscape of Parallel Computing Research: A View from Berkeley |
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| Sep 14th | Parallel Programming Introduction |
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Read: Software and the Concurrency Revolution Ref: Introduction to Parallel Computing Ref: POSIX Thread Programming Ref: MPI Tutorial |
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| Sep 16th | Parallel Programming for Performance |
| Sep 18th | Discussion on Programming Assignment |
| Sep 21st | Cache Coherence I |
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Read: P. Stenstrom.
"A Survey of Cache Coherence Schemes for Multiprocessors".
IEEE Computer, 1990. Read: D. Lenoski at al. "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessors". ISCA 1990. Ref: A. Gupta et al. "Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes". ICPP 1990.
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| Sep 23rd | Cache Coherence II |
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Review: Martin, Hill and Wood
"Token Coherence: A New Framework for Shared-Memory
Multiprocessors".
IEEE Micro, 2003. Ref: Martin, Hill and Wood Token coherence: decoupling performance and correctness ISCA 2003.
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| Sep 28th | Cache Coherence/CMP Cache Design |
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Review: Marty and Hill
"Virtual Hierarchies".
IEEE Micro, 2008. Read: Zhang and Asanovic "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors". ISCA, 2005.
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| Sep 30 | Memory Consistency Models -- Basics |
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Review: Adve and Gharachorloo Shared
Memory Consistency Models: A Tutorial WRL Research Report
95/7, 1995.
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| Oct 5th | Memory Consistency Models II -- Architectural Issues |
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Review: Blundell, Martin and Wenisch
InvisiFence: performance-transparent memory ordering in
conventional multiprocessors. ISCA 2009
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| Oct 7th | Memory Consistency Models III -- Compiler and Languages |
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Review: Boehm and Adve
Foundations of the C++ Concurrency Memory Model PLDI 2008 Listen: Adve Memory Models: The Case for Rethinking Parallel Languages and Hardware. Lecture
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| Oct 12th | Synchronization |
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Read: John M. Mellor-Crummey, Michael L. Scott.
Algorithms for Scalable Synchronization on Shared-Memory
Multiprocessors. ACM Trans. Comput. Syst. 1991
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| Oct 16th | Synchronization II |
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Review: Chapters 1 and 2. Pages 1-48. Larus and Rajwar.
Transactional Memory. Synthesis Lectures on Computer
Architecture. 2007.
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| Oct 21st | Midterm I |
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| Oct 28th | Transactional Memory I |
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| Oct 30th | Transactional Memory II |
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Review: Peter Damron, Alexandra Fedorova, Yossi Lev, Victor
Luchangco, Mark Moir, Daniel Nussbaum. Hybrid transactional memory
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| Nov 2nd | Interconnection Network I |
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| Nov 4th | Interconnection Network II |
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Read (no review): Sections 2.1 and 2.2 On-Chip Networks for Multicore Systems
Li-Shiuan Peh, Stephen W. Keckler and Sriram Vangal. In Book: Multicore Processors and Systems, Editors: Steve Keckler, Kunle Olukotun and Peter Hofstee, Springer, Sep.2009.
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| Nov 9th | Interconnection Network III : Case Studies |
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Review: Sections 2.3 to and 2.6 On-Chip Networks for Multicore Systems Li-Shiuan Peh, Stephen W. Keckler and Sriram Vangal
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| Nov 11th | Interconnection Network IV |
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Review: A Delay Model and Speculative Architecture for Pipelined RoutersPeh and Dally. IEEE Micro. 2001.
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| Nov 16th | Project Presentation |
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| Nov 18th | Thread Level Speculation |
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Sohi et al. Multiscalar Processors. ISCA 1995.
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| Nov 23rd | Evaluation Methods |
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| Nov 25th | Midterm II |
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| Nov 30th | Fault Tolerance, Isolation |
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| Dec 2nd | Architectural Support for Programmability |
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| Dec 7th, 9th, 11th | Project Presentations |
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| X | Candidates for discussion |
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Cliff Click (Azul) "Java on a 1000 Cores - Tales of Hardware / Software CoDesign". Google TechTalk Yu and Narayanasamy A Case for Interleaving Constrained Shared-Memory Multi-Processor. ISCA 2009 Hammond et al The Stanford Hydra CMP IEEE Micro 2000. Herlihy and Moss Transactional Memory: Architectural Support for Lock-Free Data Structures. ISCA 1993 Intel Larrabee: A Many-Core x86 Architecture for Visual Computing Siggraph 2008.
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