EECS 573: Advanced Topics in Computer Architecture (Fall 2019)

Class Times: Monday, Wednesday 10:30-noon, 2166 DOW

Class Web Page:  http://www.eecs.umich.edu/courses/eecs573 (Visit often!)

Instructor:  Prof. Todd Austin, 4637 BBB, austin@umich.edu
Instructor Office Hours:  Monday, Wednesday 9:30-10:30am in 4637 BBB, or by appointment.

GSI: Mark Gallagher, 2773 BBB, markgall@umich.edu
GSI Office Hours:  Mon, Wed: 3-5pm, 2680 BBB (glass lab).

Course Synopsis: A graduate-level introduction to the foundations of efficient microprocessor design. We will be studying research from the computer architecture literature. The course will focus on three "hot" topics in computer architecture: (i) reliable system design, (ii) secure and correct system design, and (iii) application-specific architectures. Special emphasis is placed on helping members of the class transition from student to researcher, through projects, presentations and class discussions.

Text: None, we will be reading papers available from the Web, they are listed below.

Class News:

• Welcome to EECS 573, good luck for the semester!
   
• Paper picks due to Prof. Austin by 11:59pm Wednesday Sept 11, 2019.  Please submit your paper presentation team (exactly two people per team), and your top three picks with each pick coming from each one of the three paper topic areas: 1) Resilient system design, 2) Secure and bug-free systems, and 3) Application-specific architectures.  Please have one team member submit your paper picks using the following web form (you can edit your submission up until the submission deadline):
  
      https://goo.gl/forms/OnfyOtM9H5JTyyri1
  
  Note: If you click on the above link and it says "You need permission.", log out of your non-UM Google account, and re-log into your UM Google account at http://google.umich.edu to access the above link.
   
• Details of the EECS 573 semester-long project are now available online: PROJECTS.txt, please read this document completely! Also, the document includes a list of suggested projects, if you are looking for ideas. One page project proposals are due (in class and via email to the professor and GSI) on Wednesday, October 2.
   
• In preparation of the upcoming EECS 573 exam, we have put the class presentations online. They are available here.
   

Course Schedule (tentative):

Project: There will be one project beginning in week 5. Students may work in pairs or groups of up to four - of course, larger groups will be expected to produce more results. Students will conduct a research project that includes a quantitative evaluation of the proposed invention.  Students will meeting with the professor to propose the project, meet during the semester for a checkpoint meeting, and finally produce a research report and present their findings in the final week of class.

Details of the project are now available online: PROJECTS.txt, please read this document completely! Also, the document includes a list of suggested projects, if you are looking for ideas. One page project proposals are due (in class and via email to the professor and GSI) on Wednesday, October 2.

Grading:

Class Participation: 10%
Class Presentation: 20%
Exam: 30%
Project: 40%

Reading List:

We will be reading many of the following papers. We will discuss them in the week specified in the table above, please have read the papers by the beginning of class.

NOTE: To view ACM and IEEE papers you must have an account with that institution OR you must access the papers from within the UMich.edu domain.  If off campus, it may be possible to authenticate with your UM unique ID and access the IEEE Xplore and ACM Digital Library using the following links:

    IEEE Xplore
    ACM Digital Library

Resilient System Design

1. Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems, E. Ozer et al, MICRO 2018.

2. The EH Model: Early Design Space Exploration of Intermittent Processor Architectures, J.S. Miguel et al, MICRO 2018.

3. IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores, K. Wang et al, ISCA 2019.
4. Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST, Ganapathy et al, HPCA 2019.
5. Architecting Waferscale Processors, Pal et al, HPCA 2019.
6. Reliability Evaluation of Mixed-Precision Architectures, Fernandes dos Santos et al, HPCA 2019.
7. Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag, Gendler et al, HPCA 2018.
8. Clank: Architectural Support for Intermittent Computation, Hicks, ISCA 2017.
9. Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices, Cha et al, HPCA 2017.
10. Reliability-Aware Scheduling on Heterogeneous Multicore Processors, Naithani et al, HPCA 2017.
11. Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators, De Oliveira et al, HPCA 2017.
12. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions, Patel et al, ISCA 2017.
13. RelaxFault Memory Repair, Dong Wan Kim and Mattan Erez, in ISCA 2016.
14. Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs, Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri Strukov, Yuan Xie, and Frederic T. Chong, ISCA 2016.
15. XED: Exposing On-Die Error Detection Information for Strong Memory Reliability, Prashant J. Nair, Vilas Sridharan, and Moinuddin K. Qureshi, ISCA 2016.
16. Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors,  A. Bacha et. al., in MICRO 2014.
17. Fine-Grained Fault Tolerance using Device Checkpoints, Kadev et. al., in ASPLOS 2013.
18. ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates, Nair et. al., in ISCA 2013.
19. The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults, Hardy et. al., in MICRO 2012.
20. NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures, Prodromou et. al., in MICRO 2012.
21. Active Management of Timing Guardband to Save Energy in POWER7, Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, and John Carter (IBM), MICRO 2011.
22. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation, Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu, ISCA 2008.
23. Blueshift: Designing processors for timing speculation from the ground up, Greskamp, B.; Lu Wan; Karpuzcu, U.R.; Cook, J.J.; Torrellas, J.; Deming Chen; Zilles, C., HPCA 2009.
24. Process Variation Tolerant 3T1D-Based Cache Architectures, Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, MICRO 2007.
25. Rescue: a microarchitecture for testability and defect tolerance, Schuchman, E.; Vijaykumar, T.N., in ISCA 2005.
26. Non-Stalling Counterflow Architecture, Michael F. Miller, Kenneth J. Janik, and Shih-Lien Lu, in HPCA-4.
    
    Secure and Bug-Free Systems
     
27. MicroScope: enabling microarchitectural replay attacks, D. Skarlatos et al, ISCA 2019.

28. InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy, M. Yan et al, MICRO 2018.

29. CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping, M.K. Qureshi, MICRO 2018.

30. POWERT Channels: A Novel Class of Covert Communication Exploiting Power Management Vulnerabilities, Khatamifard  et al, HPCA 2019.
31. FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data, Roy et al, HPCA 2019.
32. Conditional Speculation: An Effective Approach to Safeguard Out-of-Order Execution Against Spectre Attacks, Zhao et al, HPCA 2019.
33. Secure Chip Odometers Using Intentional Controlled Aging, Akkaya et al, HOST 2018.
34. A Compact Energy-Efficient Pseudo-Static Camouflaged Logic Family, Mohan et al, HOST 2018.
35. Independent Detection of Recycled Flash Memory: Challenges and Solutions, Kumari et al, HOST 2018.
36. Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols, Aysu et al, HOST 2018.
37. Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency, Taram et al, ISCA 2018.
38. Practical Memory Safety with REST, Sinha et al, ISCA 2018.
39. ASLR on the Line: Practical Cache Attacks on the MMU, Gras et al, NDSS 2017.
40. ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories, Awad et al, ISCA 2017.
41. Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures, Deng et al, ISCA 2017.
42. EDDIE: EM-Based Detection of Deviations in Program Execution, Nazari et al, ISCA 2017.
43. PoisonIvy: Safe Speculation for Secure Memory, Lehman et al, MICRO 2016.
44. Jump Over ASLR: Attacking Branch Predictors to Bypass ASLR, Evtyushkin et al, MICRO 2016.
45. Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques, Cai et al, HPCA 2017.
46. Secure Dynamic Memory Scheduling Against Timing Channel Attacks, Wang et al, HPCA 2017.
47. Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers, A. Awad et.al., ASPLOS 2016.
48. GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation, C. Liu et.al.,  ASPLOS 2015.
49. Sanctum: Minimal Hardware Extensions for Strong Software Isolation, Victor Costan et.al., in USENIX 2016.
50. Border control: sandboxing accelerators, L. E. Olson et.al., MICRO 2015.
51. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, Y. Kim, in ISCA 2014.
52. A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events, R. Callan et. al., in MICRO 2014.
53. Using Likely Invariants for Automated Software Fault Localization, Sahoo et. al., in ASPLOS 2013.
54. On the Feasibility of Online Malware Detection with Performance Counters, Demme et. al., in ISCA 2013.
55. Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors, Ren et. al., in ISCA 2013.
56. SCRAP: Architecture for Signature-Based Protection from Code Reuse Attacks, Kayaalp et. al., in HPCA 2013.
57. Reliably Erasing Data From Flash-Based Solid State Drives, Michael Wei, Laura M. Grupp, Frederick E. Spada, Steven Swanson, FAST 2011.
58. A Randomized Scheduler with Probabilistic Guarantees of Finding Bugs, Sebastian Burckhardt, Pravesh Kothari, Madanlal Musuvathi and Santosh Nagarakatte (Microsoft Research), ASPLOS 2010.
59. Entropy Extraction in Metastability-based TRNG, V. Suresh and W. Burleson, HOST 2010.
60. Designing and implementing malicious hardware, Samuel T. King, Joseph Tucek, Anthony Cozzie, Chris Grier, Weihang Jiang, and Yuanyuan Zhou, LEET 2008.
    
    Application-Specific Architectures
     
61. The Accelerator Wall: Limits of Chip Specialization, Fuchs et al, HPCA 2019.
62. Machine Learning at Facebook: Understanding Inference at the Edge, Wu et al, HPCA 2019.
63. Gables: A Roofline Model for Mobile SoCs with Many Accelerators and Ceilings, Hill et al, HPCA 2019.
64. Master of none acceleration: a comparison of accelerator architectures for analytical query processing, A. Lottarini et al, ISCA 2019.

65. Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling, A. Mukkara et al, MICRO 2018.

66. GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware, A. Samajdar et al, MICRO 2018.

67. An Experimental Microarchitecture for a Superconducting Quantum Processor, Fu et al, MICRO 2017.
68. Space-Time Algebra: A Model for Neocortical Computation, Smith, ISCA 2018.
69. GenAx: A Genome Sequencing Accelerator, Fuijiki et al, ISCA 2018.
70. PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms, Srivastava et al, ISCA 2018.
71. A Case for Packageless Processors, Pal et al, HPCA 2018.
72. Compute Caches, Aga et al, HPCA 2017.
73. SCALEDEEP: A Scalable Compute Architecture for Learning and Evaluating Deep Networks, Venkataramani et al, ISCA 2017.
74. Bespoke Processors for Applications with Ultra-low Area and Power Constraints, Cherupalli  et al, ISCA 2017.
75. Plasticine: A Reconfigurable Architecture for Parallel Patterns, Prabhakar et al, ISCA 2017.
76. Energy Efficient Architecture for Graph Analytics Accelerators, Muhammet Mustafa Ozdal , Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven Burns, and Ozcan Ozturk, ISCA 2016.
77. ASIC Clouds: Specializing the Datacenter, Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez, and Michael Bedford Taylor, ISCA 2016.
78. MaPU: A novel mathematical computing architecture, Donglin Wang et al., HPCA 2016.
79. TABLA: A unified template-based framework for accelerating statistical machine learning, Divya Mahajan et al, HPCA 2016.
80. An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks, Mingu Kang et al, ICASSP 2015.
81. HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing, Mingyu Gao and Christos Kozyrakis, HPCA 2016.
82. General-Purpose Code Acceleration with Limited-Precision Analog Computation, R. St. Amant et. al., in ISCA 2014.
83. Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures, Shao et. al., in ISCA 2014.
84. Understanding sources of inefficiency in general-purpose chips, Hameed et al., in ISCA 2010.
85. LINQits: big data on little clients, Chung et al., in ISCA 2013.
86. STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution, Atta et al., in ISCA 2013.
87. Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing, Qadeer et. al., in ISCA 2013.
88. Neural Acceleration for General-Purpose Approximate Programs, Esmaeilzadeh et. al., in MICRO 2012.
89. Architecture Support for Disciplined Approximate Programming. Hadi Esmaeilzadeh (University of Washington), Adrian Sampson (University of Washington), Luis Ceze (University of Washington) and Doug Burger (Microsoft Research), ASPLOS 2012.
    
    Additional papers covered in lecture:
     
90. A Case for Unlimited Watchpoints. Joseph Greathouse (University of Michigan), Hongyi Xin (University of Michigan/SJTU), Yixin Luo (University of Michigan/SJTU) and Todd Austin (University of Michigan), ASPLOS 2012.
91. EFFEX: an embedded processor for computer vision bSased feature extraction, Jason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin, DAC 2011.
92. Fault-Based Attack of RSA Authentication, Andrea Pellegrini, Valeria Bertacco and Todd Austin, in the 2010 Design, Automation and Test in Europe Conference (DATE-2010), March 2010.
93. Razor: a low-power pipeline based on circuit-level timing speculation, Ernst, D.; Nam Sung Kim; Das, S.; Pant, S.; Rao, R.; Toan Pham; Ziesler, C.; Blaauw, D.; Austin, T.; Flautner, K.; Mudge, T., in MICRO 2003.
94. Energy optimization of subthreshold-voltage sensor network processors, Nazhandali, L.; Zhai, B.; Olson, A.; Reeves, A.; Minuth, M.; Helfand, R.; Sanjay Pant; Austin, T.; Blaauw, D., in ISCA 2005.
95. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Mukherjee, S.S.; Weaver, C.; Emer, J.; Reinhardt, S.K.; Austin, T., in MICRO 2003.
96. Ultra Low-Cost Defect Protection for Microprocessor Pipelines, Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin, in ASPLOS 2006.
97. Architectural implications of brick and mortar silicon manufacturing, Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd Austin, ISCA 2007.
98. Testudo: Heavyweight security analysis via statistical sampling, Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco, Seth Pettie, MICRO 2008.
99. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
    Kypros Constantinides, Onur Mutlu, Todd Austin, Valeria Bertacco, MICRO 2007.