EECS 573: Microarchitecture (Fall 2010)

Instructor:  Todd Austin, CSE 4637, austin@umich.edu

Class Times: Monday, Wednesday 10:30-noon, 1371 GGBL

Office Hours:  Monday, Wednesday 9:30-10:30, or by appt.

Class Web Page:  http://www.eecs.umich.edu/courses/eecs573    (Visit often!)

Course Synopsis:  A graduate-level introduction to the foundations of efficient microprocessor designs. Problems involving instruction supply, data supply, and instruction processing, compile-time vs. run-time tradeoffs, and in-order vs. out-of-order execution. Special focus is placed on reliability, security, and application-specific design. Case studies are taken from current microprocessors.

Text:  None, we will be reading papers available from the Web, they are listed below.

News:

• 09/07/2010: Welcome to EECS 573, and good luck for the semester!
• 09/08/2010: Paper requests are due to the instructor (via e-mail) by end-of-day Monday September 13th. Please select 6 candidate papers to present, two from each of the three topic areas (i.e., Resilient System Design, Secure and Bug-Free Systems, and Application-Specific Architectures). You will end up presenting one of your selected candidate papers. A class schedule will be made from selected papers, and it will be published on this website in the second week of class.
• 10/09/2010: The project list (and details on the EECS 573 projects) have been released, get them here: PROJECTS.txt
• 11/28/2010: A sample exam (from a previous semester of EECS 573) is available: exam573-sample.pdf
• 12/5/2010: Class project presentations are Thursday, December 9, 3-7pm in CSE 3725, sign up for a presentation time in class on Monday 12/6/2010

Course Schedule (tentative):

Project:  There will be one project beginning in week 4. Students may work in pairs or groups of three - of course, larger groups will be expected to produce more results. Students will conduct a research project that includes a quantitative evaluation of the proposed invention.  Students will meeting with the professor to propose the project, meet during the semester for a checkpoint meeting, and finally produce a research report and present their findings in the final week of class.

Details of the project can be found here: PROJECTS.txt

Some class projects may choose to utilize the SimpleScalar Tool Set for their project.  The SimpleScalar sources and class-sized benchmarks are available here:

  http://www.simplescalar.com/tools.html (use the 3v0d version)
  http://www.eecs.umich.edu/courses/eecs573/public/instruct-progs.tar.gz

Grading:

Class Participation: 10%\
Class Presentation: 20%
Exam: 30%
Project: 40%

Lectures:

1. Lecture 01 - Class presentation overview
2. Lecture 02 - Robust Computing Tutorial
3. Lecture 03 - Secure and Correct Systems Tutorial
4. Lecture 04 - Application-Specific Design

Reading List:           

We will be reading the following papers. We will discuss them in the week specified in the table above, please have read the papers by the beginning of class.

NOTE: To view ACM and IEEE papers you must have an account with that institution OR you must access the papers from within the UMich.edu domain.  If off campus, it may be possible to authenticate with your UM unique ID and access the IEEE Xplore and ACM Digital Library using the following links:

    IEEE Xplore
    ACM Digital Library

Resilient System Design

1. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation, Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu, ISCA 2008.
2. ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency, Xiaoyao Liang, Gu-Yeon Wei, David Brooks, ISCA 2008.
3. Voltage emergency prediction: Using signatures to reduce operating margins, Reddi, V.J.; Gupta, M.S.; Holloway, G.; Gu-Yeon Wei; Smith, M.D.; Brooks, D., HPCA 2009.
4. Accurate microarchitecture-level fault modeling for studying hardware faults, Man-Lap Li; Ramachandran, P.; Karpuzcu, U.R.; Hari, S.; Adve, S.V., HPCA 2009.
5. Blueshift: Designing processors for timing speculation from the ground up, Greskamp, B.; Lu Wan; Karpuzcu, U.R.; Cook, J.J.; Torrellas, J.; Deming Chen; Zilles, C., HPCA 2009.
6. Relax: An Architectural Framework for Software Recovery of Hardware Faults, Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam, in ISCA 2010.
7. Perturbation-based Fault Screening, Racunas, P.; Constantinides, K.; Manne, S.; Mukherjee, S.S., HPCA 2007.
8. The StageNet fabric for constructing resilient multicore systems, Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason Blome, Scott Mahlke, MICRO 2008.
9. A performance-correctness explicitly-decoupled architecture, Alok Garg, Michael C. Huang, MICRO 2008.
10. Process Variation Tolerant 3T1D-Based Cache Architectures, Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, MICRO 2007.
11. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores, Albert Meixner, Michael E. Bauer, Daniel Sorin, MICRO 2007.
12. Leveraging 3D Technology for Improved Reliability, Niti Madan, Rajeev Balasubramonian, MICRO 2007.
13. Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs, Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori, in HPCA 2010.
14. Rescue: a microarchitecture for testability and defect tolerance, Schuchman, E.; Vijaykumar, T.N., in ISCA 2005.
15. Exploiting structural duplication for lifetime reliability enhancement, Srinivasan, J.; Adve, S.V.; Pradip Bose; Rivers, J.A., in ISCA 2005.
16. Techniques to reduce the soft error rate of a high-performance microprocessor, Weaver, C.; Emer, J.; Mukherjee, S.S.; Reinhardt, S.K., in ISCA 2004.
17. A mechanism for online diagnosis of hard faults in microprocessors, Bower, F.A.; Sorin, D.J.; Ozev, S., in MICRO 2005.
18. A defect tolerant self-organizing nanoscale SIMD architecture, Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck, in ASPLOS 2006.
19. Fingerprinting: bounding soft-error detection latency and bandwidth, Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk, in ASPLOS 2004.
20. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors, Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), in MICRO-35.
21. Non-Stalling Counterflow Architecture, Michael F. Miller, Kenneth J. Janik, and Shih-Lien Lu, in HPCA-4.

Secure and Bug-Free Systems

22. SigRace: signature-based data race detection, Abdullah Muzahid, Dario Suárez, Shanxiang Qi, Josep Torrellas, ISCA 2009.
23. A case for an interleaving constrained shared-memory multi-processor, Jie Yu, Satish Narayanasamy, ISCA 2009.
24. Atom-Aid: Detecting and Surviving Atomicity Violations, Brandon Lucia, Joseph Devietti, Karin Strauss, Luis Ceze, ISCA 2008.
25. Security Refresh: Prevent Malicious Wear-out and Increase Durability for Phase-Change Memory with Dynamically Randomized Address Mapping, Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee, in ISCA 2010.
26. Raksha: a flexible information flow architecture for software security, Michael Dalton, Hari Kannan, Christos Kozyrakis, ISCA 2007.
27. New cache designs for thwarting software cache-based side channel attacks, Zhenghong Wang, Ruby B. Lee, ISCA 2007.
28. Dacota: Post-silicon validation of the memory subsystem in multi-core designs, DeOrio, A.; Wagner, I.; Bertacco, V., HPCA 2009.
29. FlexiTaint: A programmable accelerator for dynamic taint propagation, Venkataramani, G.; Doudalis, I.; Solihin, Y.; Prvulovic, M., HPCA 2008.
30. MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging, Venkataramani, G.; Roemer, B.; Solihin, Y.; Prvulovic, M., HPCA 2007.
31. InfoShield: a security architecture for protecting information usage in memory, Shi, W.; Fryman, J.B.; Gu, G.; Lee, H.-H.S.; Zhang, Y.; Yang, J., HPCA 2006.
32. Control flow obfuscation with information flow tracking, Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang, Pen-chung Yew, MICRO 2009.
33. SHARK: Architectural support for autonomic protection against stealth by rootkit exploits, Vikas R. Vasisht, Hsien-Hsin S. Lee, MICRO 2008.
34. IVEC: Off-Chip Memory Integrity Protection for Both Security and Reliability, Ruirui Huang, G. Edward Suh, in ISCA 2010..
35. Architecture for protecting critical secrets in microprocessors, Lee, R.B.; Kwan, P.C.S.; McGregor, J.P.; Dwoskin, J.; Zhenghong Wang, in ISCA 2005.
36. Design and implementation of the AEGIS single-chip secure processor using physical random functions, Suh, G.E.; O'Donnell, C.W.; Ishan Sachdev; Srinivas Devadas, in ISCA 2005.
37. A Hardware-Software Platform for Intrusion Prevention, Drinic, M.; Kirovski, D., in MICRO 2004.
38. RIFLE: An Architectural Framework for User-Centric Information-Flow Security, Vachharajani, N.; Bridges, M.J.; Chang, J.; Rangan, R.; Ottoni, G.; Blome, J.A.; Reis, G.A.; Vachharajani, M.; August, D.I., in MICRO 2004.
39. Secure program execution via dynamic information flow tracking, G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas, in ASPLOS 2004.
40. Mondrian memory protection, Emmett Witchel, Josh Cates, Krste Asanović, in ASPLOS 2002.
41. Scalable Architectural Support for Trusted Software, David Champagne, Ruby Lee, in HPCA 2010.
42. Recovery domains: an organizing principle for recoverable operating systems, Andrew Lenharth, Vikram S. Adve, Samuel T. King, ASPLOS 2009.
43. Efficient online validation with delta execution, Joseph Tucek, Weiwei Xiong, Yuanyuan Zhou, ASPLOS 2009.
44. Leak pruning, Michael D. Bond, Kathryn S. McKinley, ASPLOS 2009.
45. Hardbound: architectural support for spatial safety of the C programming language, Joe Devietti, Colin Blundell, Milo M. K. Martin, Steve Zdancewic, ASPLOS 2008.
46. Archipelago: trading address space for reliability and security, Vitaliy B. Lvin, Gene Novark, Emery D. Berger, Benjamin G. Zorn, ASPLOS 2008.

Application-Specific Architectures

47. AnySP: anytime anywhere anyway signal processing, Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner, ISCA 2009.
48. Rigel: an architecture and scalable programming interface for a 1000-core accelerator, John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel, ISCA 2009.
49. 3D-Stacked Memory Architectures for Multi-core Processors, Gabriel H. Loh, ISCA 2008.
50. Anton, a special-purpose machine for molecular dynamics simulation, David E. Shaw and et al, ISCA 2007.
51. ParallAX: an architecture for real-time physics, Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman, ISCA 2007.
52. Optical Interconnect Opportunities for Future Server Memory Systems, Katayama, Y.; Okazaki, A., HPCA 2007.
53. Tradeoffs in designing accelerator architectures for visual computing, Aqeel Mahesri, Daniel Johnson, Neal Crago, Sanjay J. Patel, MICRO 2008.
54. Toward a multicore architecture for real-time ray-tracing, Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary Vernon, William R. Mark, MICRO 2008.
55. SODA: A Low-power Architecture For Software Radio, Yuan Lin; Hyunseok Lee; Woh, M.; Harel, Y.; Mahlke, S.; Mudge, T.; Chakrabarti, C.; Flautner, K., in ISCA 2006.
56. A Dynamically Configurable Coprocessor for Convolutional Neural Networks, Srimat Chakradhar, Murugan Sankaradas, Venkata Jakkula, Srihari Cadambi, in ISCA 2010.
57. A high throughput string matching architecture for intrusion detection and prevention, Lin Tan; Sherwood, T., in ISCA 2005.
58. An architecture framework for transparent instruction set customization in embedded processors, Clark, N.; Blome, J.; Chu, M.; Mahlke, S.; Biles, S.; Flautner, K., in ISCA 2005.
59. Processor acceleration through automated instruction set customization, Clark, N.; Hongtao Zhong; Mahlke, S., in MICRO 2003.
60. Energy Proportional Datacenter Networks, Dennis Abts, Mike Marty, Philip Wells, Peter Klausler, Hong Liu, in ISCA 2010.

Additional papers covered in lecture:

61. Razor: a low-power pipeline based on circuit-level timing speculation, Ernst, D.; Nam Sung Kim; Das, S.; Pant, S.; Rao, R.; Toan Pham; Ziesler, C.; Blaauw, D.; Austin, T.; Flautner, K.; Mudge, T., in MICRO 2003.
62. Energy optimization of subthreshold-voltage sensor network processors, Nazhandali, L.; Zhai, B.; Olson, A.; Reeves, A.; Minuth, M.; Helfand, R.; Sanjay Pant; Austin, T.; Blaauw, D., in ISCA 2005.
63. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Mukherjee, S.S.; Weaver, C.; Emer, J.; Reinhardt, S.K.; Austin, T., in MICRO 2003.
64. Ultra Low-Cost Defect Protection for Microprocessor Pipelines, Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin, in ASPLOS 2006.
65. Architectural implications of brick and mortar silicon manufacturing, Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd Austin, ISCA 2007.
66. Testudo: Heavyweight security analysis via statistical sampling, Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco, Seth Pettie, MICRO 2008.
67. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
    Kypros Constantinides, Onur Mutlu, Todd Austin, Valeria Bertacco, MICRO 2007.

Presentation Schedule: