EECS 573: Microarchitecture (Fall 2016)

Class Times: Monday, Wednesday 10:30-noon, 2166 DOW

Class Web Page:  http://www.eecs.umich.edu/courses/eecs573 (Visit often!)

 

Instructor:  Todd Austin, 4637 BBB, austin@umich.edu
Instructor Office Hours:  Monday, Wednesday 9:30-10:30am, 4637 BBB, or by appointment.

GSI: Patipan Prasertsom, 2773 BBB, pprasert@umich.edu
GSI Office Hours:  Monday, Thursday 1:30-3:00pm, 2773 BBB.

 

Course Synopsis: A graduate-level introduction to the foundations of efficient microprocessor design. We will be studying research from the computer architecture literature. The course will focus on three "hot" topics in computer architecture: (i) reliable system design, (ii) secure and correct system design, and (iii) application-specific architectures. Special emphasis is placed on helping members of the class transition from student to researcher, through projects, presentations and class discussions.

Text: None, we will be reading papers available from the Web, they are listed below.

Class News:

Course Schedule (tentative):

 

DATE CLASS TOPIC CLASS READINGS CLASS EVENTS
Wed 9/07/2016   1 Introduction, What is research? Lecture #1 Paper list published
Mon 9/12/2016   2 Resilient System Design - Intro Lecture #2 Select teams/papers by end-of-day 9/12
Wed 9/14/2016   3 Resilient System Design - Intro Lecture #3  
Mon 9/19/2016   4 Resilient System Design - Example Paper Paper #67  
Wed 9/21/2016 5 Resilient System Design - Papers Paper #1 (wpehrett/timlinsc)
Mon 9/26/2016   6 Resilient System Design - Papers Paper #13 (rovinski/krjgsmth), Paper #5 (ankwong/mcbolto)  
Wed 9/28/2016   7 Resilient System Design - Papers Paper #19 (skachm/shihclin)  
Mon 10/03/2016   8 Resilient System Design - Papers Paper #15 (llanlan/zhefanye)  
Wed 10/05/2016   9 Secure and Bug-Free Systems - Intro Lecture #4

Receive project details
Mon 10/10/2016   10 Secure and Bug-Free Systems - Intro Lecture #5  
Wed 10/12/2016   11 Secure and Bug-Free Systems - Papers Paper #31 (jeeheh/wfchen) Project proposals due, one page, in class
Mon 10/17/2016   no class      
Wed 10/19/2016   12 Secure and Bug-Free Systems - Papers Paper #38 (marver/Bradengl), Paper #36 (kdesingh/zsui)

(Patipan leads class.)
Mon 10/24/2016   no class      
Wed 10/26/2016 14 Secure and Bug-Free Systems - Papers Paper #27 (wenctsai/nahmadi)

 
Mon 10/31/2016   15 Secure and Bug-Free Systems - Papers Paper #33 (harvv/subh) Project checkpoint meetings, 1-pg report due
Wed 11/02/2016   16 Application-Specific Archs - Intro Lecture #6  
Mon 11/07/2016 17 Application-Specific Archs - Special Topic Lecture #7 (Patipan teaching class, topic: Composable Customization.)
Wed 11/09/2016   18 Application-Specific Archs - Papers Paper #50 (taeju/sunggg)  
Mon 11/14/2016   19 Application-Specific Archs - Papers Paper #52 (stroud/preetir), Paper #47 (jbaile/shikaili)  
Wed 11/16/2016   20 Application-Specific Archs - Papers Paper #44 (aditysha/akhilar), Paper #53 (ezhilrmb/rashmivs)  
Mon 11/21/2016   21 Application-Specific Archs - Papers Paper #54 (sagnik/schepel) Project checkpoint meetings, 1-pg report due
Wed 11/23/2016   no class      
Mon 11/28/2016   22 Exam Review Exam Review (practice exam available)  
Wed 11/30/2016   23 Exam   Exam 11/30, in class, open notes
Mon 12/05/2016   24 Extended project office hours in 4637 BBB    
Wed 12/07/2016   25 Project presentations (extended class)   Class project presentations, from noon-4pm, location TBD
Mon 12/12/2016   26 Project reports due   Reports due 12/12 by end-of-day

Project: There will be one project beginning in week 5. Students may work in pairs or groups of up to four - of course, larger groups will be expected to produce more results. Students will conduct a research project that includes a quantitative evaluation of the proposed invention.  Students will meeting with the professor to propose the project, meet during the semester for a checkpoint meeting, and finally produce a research report and present their findings in the final week of class.

Details of the project will be available shortly before the project starts.

Some class projects may choose to utilize the SimpleScalar Tool Set for their project.  The SimpleScalar sources and class-sized benchmarks are available here:

  http://www.simplescalar.com/tools.html (use the 3v0e version)
  http://www.eecs.umich.edu/courses/eecs573/public/instruct-progs.tar.gz

Grading:

Class Participation: 10%
Class Presentation: 20%
Exam: 30%
Project: 40%

Lectures:

  1. Lecture 01 - Class overview
  2. Lecture 02/03 - Resilient System Design Tutorial

Reading List:

We will be reading many of the following papers. We will discuss them in the week specified in the table above, please have read the papers by the beginning of class.

NOTE: To view ACM and IEEE papers you must have an account with that institution OR you must access the papers from within the UMich.edu domain.  If off campus, it may be possible to authenticate with your UM unique ID and access the IEEE Xplore and ACM Digital Library using the following links:

    IEEE Xplore
    ACM Digital Library

Resilient System Design

  1. RelaxFault Memory Repair, Dong Wan Kim and Mattan Erez, in ISCA 2016.
  2. Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs, Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri Strukov, Yuan Xie, and Frederic T. Chong, ISCA 2016.
  3. XED: Exposing On-Die Error Detection Information for Strong Memory Reliability, Prashant J. Nair, Vilas Sridharan, and Moinuddin K. Qureshi, ISCA 2016.
  4. Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors,  A. Bacha et. al., in MICRO 2014.
  5. Avoiding Core's DUE & SDC via Acoustic Wave Detectors and Tailored Error Containment and Recovery, Upasani  et. al., in ISCA 2014.
  6. Fine-Grained Fault Tolerance using Device Checkpoints, Kadev et. al., in ASPLOS 2013.
  7. ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates, Nair et. al., in ISCA 2013.
  8. Resilient Die-stacked DRAM Caches, Sim et. al., in ISCA 2013.
  9. The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults, Hardy et. al., in MICRO 2012.
  10. NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures, Prodromou et. al., in MICRO 2012.
  11. Active Management of Timing Guardband to Save Energy in POWER7, Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, and John Carter (IBM), MICRO 2011.
  12. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation, Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu, ISCA 2008.
  13. Voltage emergency prediction: Using signatures to reduce operating margins, Reddi, V.J.; Gupta, M.S.; Holloway, G.; Gu-Yeon Wei; Smith, M.D.; Brooks, D., HPCA 2009.
  14. Blueshift: Designing processors for timing speculation from the ground up, Greskamp, B.; Lu Wan; Karpuzcu, U.R.; Cook, J.J.; Torrellas, J.; Deming Chen; Zilles, C., HPCA 2009.
  15. Perturbation-based Fault Screening, Racunas, P.; Constantinides, K.; Manne, S.; Mukherjee, S.S., HPCA 2007.
  16. Process Variation Tolerant 3T1D-Based Cache Architectures, Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, MICRO 2007.
  17. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores, Albert Meixner, Michael E. Bauer, Daniel Sorin, MICRO 2007.
  18. Rescue: a microarchitecture for testability and defect tolerance, Schuchman, E.; Vijaykumar, T.N., in ISCA 2005.
  19. A mechanism for online diagnosis of hard faults in microprocessors, Bower, F.A.; Sorin, D.J.; Ozev, S., in MICRO 2005.
  20. Non-Stalling Counterflow Architecture, Michael F. Miller, Kenneth J. Janik, and Shih-Lien Lu, in HPCA-4.

    Secure and Bug-Free Systems
     
  21. Authenticache: Harnessing Cache ECC for System Authentication, Anys Bacha et.al., MICRO 2015.
  22. Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers, A. Awad et.al., ASPLOS 2016.
  23. GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation, C. Liu et.al.,  ASPLOS 2015.
  24. Sanctum: Minimal Hardware Extensions for Strong Software Isolation, Victor Costan et.al., in USENIX 2016.
  25. Border control: sandboxing accelerators, L. E. Olson et.al., MICRO 2015.
  26. Cache Storage Channels: Alias-Driven Attacks and Verified Countermeasures, R. Guanciale et.al., IEEE SP 2016.
  27. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, Y. Kim, in ISCA 2014.
  28. A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events, R. Callan et. al., in MICRO 2014.
  29. InkTag: Secure Applications on an Untrusted Operating System, Hofmann et. al., in ASPLOS 2013.
  30. Using Likely Invariants for Automated Software Fault Localization, Sahoo et. al., in ASPLOS 2013.
  31. On the Feasibility of Online Malware Detection with Performance Counters, Demme et. al., in ISCA 2013.
  32. Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors, Ren et. al., in ISCA 2013.
  33. SCRAP: Architecture for Signature-Based Protection from Code Reuse Attacks, Kayaalp et. al., in HPCA 2013.
  34. Reliably Erasing Data From Flash-Based Solid State Drives, Michael Wei, Laura M. Grupp, Frederick E. Spada, Steven Swanson, FAST 2011.
  35. A Randomized Scheduler with Probabilistic Guarantees of Finding Bugs, Sebastian Burckhardt, Pravesh Kothari, Madanlal Musuvathi and Santosh Nagarakatte (Microsoft Research), ASPLOS 2010.
  36. Entropy Extraction in Metastability-based TRNG, V. Suresh and W. Burleson, HOST 2010.
  37. A case for an interleaving constrained shared-memory multi-processor, Jie Yu, Satish Narayanasamy, ISCA 2009.
  38. Designing and implementing malicious hardware, Samuel T. King, Joseph Tucek, Anthony Cozzie, Chris Grier, Weihang Jiang, and Yuanyuan Zhou, LEET 2008.
  39. Control flow obfuscation with information flow tracking, Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang, Pen-chung Yew, MICRO 2009.
  40. Hardbound: architectural support for spatial safety of the C programming language, Joe Devietti, Colin Blundell, Milo M. K. Martin, Steve Zdancewic, ASPLOS 2008.

    Application-Specific Architectures
     
  41. Energy Efficient Architecture for Graph Analytics Accelerators, Muhammet Mustafa Ozdal , Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven Burns, and Ozcan Ozturk, ISCA 2016.
  42. ASIC Clouds: Specializing the Datacenter, Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez, and Michael Bedford Taylor, ISCA 2016.
  43. MaPU: A novel mathematical computing architecture, Donglin Wang et al., HPCA 2016.
  44. TABLA: A unified template-based framework for accelerating statistical machine learning, Divya Mahajan et al, HPCA 2016.
  45. Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses, Vivek Seshadri et al, MICRO 2015.
  46. An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks, Mingu Kang et al, ICASSP 2015.
  47. HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing, Mingyu Gao and Christos Kozyrakis, HPCA 2016.
  48. General-Purpose Code Acceleration with Limited-Precision Analog Computation, R. St. Amant et. al., in ISCA 2014.
  49. Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures, Shao et. al., in ISCA 2014.
  50. HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs, Campanoni  et.al., in ISCA 2014.
  51. Understanding sources of inefficiency in general-purpose chips, Hameed et al., in ISCA 2010.
  52. LINQits: big data on little clients, Chung et al., in ISCA 2013.
  53. STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution, Atta et al., in ISCA 2013.
  54. Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing, Qadeer et. al., in ISCA 2013.
  55. Neural Acceleration for General-Purpose Approximate Programs, Esmaeilzadeh et. al., in MICRO 2012.
  56. Architecture Support for Disciplined Approximate Programming. Hadi Esmaeilzadeh (University of Washington), Adrian Sampson (University of Washington), Luis Ceze (University of Washington) and Doug Burger (Microsoft Research), ASPLOS 2012.
  57. Rigel: an architecture and scalable programming interface for a 1000-core accelerator, John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel, ISCA 2009.
  58. Anton, a special-purpose machine for molecular dynamics simulation, David E. Shaw and et al, ISCA 2007.
  59. ParallAX: an architecture for real-time physics, Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman, ISCA 2007.
  60. SODA: A Low-power Architecture For Software Radio, Yuan Lin; Hyunseok Lee; Woh, M.; Harel, Y.; Mahlke, S.; Mudge, T.; Chakrabarti, C.; Flautner, K., in ISCA 2006.

    Additional papers covered in lecture:
     
  61. A Case for Unlimited Watchpoints. Joseph Greathouse (University of Michigan), Hongyi Xin (University of Michigan/SJTU), Yixin Luo (University of Michigan/SJTU) and Todd Austin (University of Michigan), ASPLOS 2012.
  62. EFFEX: an embedded processor for computer vision bSased feature extraction, Jason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin, DAC 2011.
  63. Fault-Based Attack of RSA Authentication, Andrea Pellegrini, Valeria Bertacco and Todd Austin, in the 2010 Design, Automation and Test in Europe Conference (DATE-2010), March 2010.
  64. Razor: a low-power pipeline based on circuit-level timing speculation, Ernst, D.; Nam Sung Kim; Das, S.; Pant, S.; Rao, R.; Toan Pham; Ziesler, C.; Blaauw, D.; Austin, T.; Flautner, K.; Mudge, T., in MICRO 2003.
  65. Energy optimization of subthreshold-voltage sensor network processors, Nazhandali, L.; Zhai, B.; Olson, A.; Reeves, A.; Minuth, M.; Helfand, R.; Sanjay Pant; Austin, T.; Blaauw, D., in ISCA 2005.
  66. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Mukherjee, S.S.; Weaver, C.; Emer, J.; Reinhardt, S.K.; Austin, T., in MICRO 2003.
  67. Ultra Low-Cost Defect Protection for Microprocessor Pipelines, Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin, in ASPLOS 2006.
  68. Architectural implications of brick and mortar silicon manufacturing, Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd Austin, ISCA 2007.
  69. Testudo: Heavyweight security analysis via statistical sampling, Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco, Seth Pettie, MICRO 2008.
  70. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
    Kypros Constantinides, Onur Mutlu, Todd Austin, Valeria Bertacco, MICRO 2007.