EECS 573: Microarchitecture (Fall 2014)

Instructor:  Todd Austin, CSE 4637, austin@umich.edu

Class Times: Monday, Wednesday 10:30-noon, 2166 DOW

Office Hours:  Monday, Wednesday 9:30-10:30am, 4637 BBB, or by appt.

Class Web Page:  http://www.eecs.umich.edu/courses/eecs573 (Visit often!)

Course Synopsis: A graduate-level introduction to the foundations of efficient microprocessor designs. We will be studying research from the computer architecture literature. The course will focus on three "hot" topics in computer architecture: (i) reliable system design, (ii) secure system design, and (iii) application-specific architectures. Special emphasis is placed on helping members of the class transition from student to researcher, through projects, presentations and class discussions.

Text: None, we will be reading papers available from the Web, they are listed below.

News:

• Welcome to EECS 573, good luck for the semester!
   
• Paper picks due to Prof. Austin by 11:59pm Monday Sept 8, 2014.  Please submit your paper presentation team (exactly two people per team), and your top three picks with each pick coming from each one of the three paper topic areas: 1) Resilient system design, 2) Secure and Bug-free systems, and 3) Application-specific architectures.  Please have one team member submit your paper picks using the following web form (you can edit your submission up until the submission deadline):
  
      https://docs.google.com/a/umich.edu/forms/d/1NJzOX85y4bTty0T0G-qnuUv3r5rQePpHT9Opu2XvQKw/viewform?usp=send_form
  
  Note: If you click on the above link and it says "You need permission.", log out of your non-UM Google account, and re-log into your UM Google account at http://google.umich.edu to access the above link.
   
• Project details have been published, and your project proposal is due in class on October 8, details of the project can be found here: PROJECT.txt
   
• The exam is Monday Nov 24 @ 10:30am (in class), open note, open book, open computer (but closed network), and here is last years exam to study from: practice exam.  Good luck to everyone!
   

Course Schedule (tentative):

Project: There will be one project beginning in week 4. Students may work in pairs or groups of up to four - of course, larger groups will be expected to produce more results. Students will conduct a research project that includes a quantitative evaluation of the proposed invention.  Students will meeting with the professor to propose the project, meet during the semester for a checkpoint meeting, and finally produce a research report and present their findings in the final week of class.

Details of the project can be found here: PROJECTS.txt

Some class projects may choose to utilize the SimpleScalar Tool Set for their project.  The SimpleScalar sources and class-sized benchmarks are available here:

  http://www.simplescalar.com/tools.html (use the 3v0e version)
  http://www.eecs.umich.edu/courses/eecs573/public/instruct-progs.tar.gz

Grading:

Class Participation: 10%
Class Presentation: 20%
Exam: 30%
Project: 40%

Lectures:

1. Lecture 01 - Class overview
2. Lecture 02 - Robust Design Tutorial
3. Lecture 03 - Robust Design Tutorial
4. Lecture 04 - Secure Systems Tutorial
5. Lecture 05 - Secure Systems Tutorial
6. Lecture 06 - Application-Specific Architectures
7. Lecture 07 - Data Parallel Architectures: GPUs

Reading List:

We will be reading many of the following papers. We will discuss them in the week specified in the table above, please have read the papers by the beginning of class.

NOTE: To view ACM and IEEE papers you must have an account with that institution OR you must access the papers from within the UMich.edu domain.  If off campus, it may be possible to authenticate with your UM unique ID and access the IEEE Xplore and ACM Digital Library using the following links:

    IEEE Xplore
    ACM Digital Library

Resilient System Design

1. Fine-Grained Fault Tolerance using Device Checkpoints, Kadev et. al., in ASPLOS 2013.
2. ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates, Nair et. al., in ISCA 2013.
3. Resilient Die-stacked DRAM Caches, Sim et. al., in ISCA 2013.
4. The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults, Hardy et. al., in MICRO 2012.
5. NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures, Prodromou et. al., in MICRO 2012.
6. Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling, Mahmood et. al., in HPCA 2013.
7. Active Management of Timing Guardband to Save Energy in POWER7, Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, and John Carter (IBM), MICRO 2011.
8. ARIADNE: Agnostic Reconfiguration In A Disconnected Network Environment, Aisopos et. al., in PACT 2011.
9. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation, Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu, ISCA 2008.
10. ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency, Xiaoyao Liang, Gu-Yeon Wei, David Brooks, ISCA 2008.
11. Voltage emergency prediction: Using signatures to reduce operating margins, Reddi, V.J.; Gupta, M.S.; Holloway, G.; Gu-Yeon Wei; Smith, M.D.; Brooks, D., HPCA 2009.
12. Accurate microarchitecture-level fault modeling for studying hardware faults, Man-Lap Li; Ramachandran, P.; Karpuzcu, U.R.; Hari, S.; Adve, S.V., HPCA 2009.
13. Blueshift: Designing processors for timing speculation from the ground up, Greskamp, B.; Lu Wan; Karpuzcu, U.R.; Cook, J.J.; Torrellas, J.; Deming Chen; Zilles, C., HPCA 2009.
14. Perturbation-based Fault Screening, Racunas, P.; Constantinides, K.; Manne, S.; Mukherjee, S.S., HPCA 2007.
15. The StageNet fabric for constructing resilient multicore systems, Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason Blome, Scott Mahlke, MICRO 2008.
16. Process Variation Tolerant 3T1D-Based Cache Architectures, Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, MICRO 2007.
17. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores, Albert Meixner, Michael E. Bauer, Daniel Sorin, MICRO 2007.
18. Design and evaluation of hybrid fault-detection systems, Reis, G.A. Chang, J. Vachharajani, N. Mukherjee, S.S. Rangan, R. August, D.I., in ISCA 2005.
19. Rescue: a microarchitecture for testability and defect tolerance, Schuchman, E.; Vijaykumar, T.N., in ISCA 2005.
20. A mechanism for online diagnosis of hard faults in microprocessors, Bower, F.A.; Sorin, D.J.; Ozev, S., in MICRO 2005.
21. Fingerprinting: bounding soft-error detection latency and bandwidth, Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk, in ASPLOS 2004.
22. Non-Stalling Counterflow Architecture, Michael F. Miller, Kenneth J. Janik, and Shih-Lien Lu, in HPCA-4.
    Secure and Bug-Free Systems
     
23. InkTag: Secure Applications on an Untrusted Operating System, Hofmann et. al., in ASPLOS 2013.
24. Verifying Security Invariants in ExpressOS, Mai et. al., in ASPLOS 2013.
25. Production-Run Software Failure Diagnosis via Hardware Performance Counters, Arulraj et. al., in ASPLOS 2013.
26. Using Likely Invariants for Automated Software Fault Localization, Sahoo et. al., in ASPLOS 2013.
27. On the Feasibility of Online Malware Detection with Performance Counters, Demme et. al., in ISCA 2013.
28. Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors, Ren et. al., in ISCA 2013.
29. SCRAP: Architecture for Signature-Based Protection from Code Reuse Attacks, Kayaalp et. al., in HPCA 2013.
30. Adaptive Reliability Chipkill Correct (ARCC), Jian et. al., in HPCA 2013.
31. RCDC: A Relaxed-Consistency Deterministic Computer, Joseph Devietti, Jacob Nelson, Tom Bergan, Luis Ceze, Dan Grossman University of Washington, ASPLOS 2011.
32. Reliable and Efficient PUF Key Generation Using Pattern Matching, Srini Devadas and Zdenek Paral (MIT), HOST 2011.
33. Reliably Erasing Data From Flash-Based Solid State Drives, Michael Wei, Laura M. Grupp, Frederick E. Spada, Steven Swanson, FAST 2011.
34. A Randomized Scheduler with Probabilistic Guarantees of Finding Bugs, Sebastian Burckhardt, Pravesh Kothari, Madanlal Musuvathi and Santosh Nagarakatte (Microsoft Research), ASPLOS 2010.
35. Entropy Extraction in Metastability-based TRNG, V. Suresh and W. Burleson, HOST 2010.
36. Orthrus: Efficient Software Integrity Protection on Multi-Cores, Ruirui Huang, Dan Deng and G. Edward Suh (Cornell University), ASPLOS 2010.
37. SigRace: signature-based data race detection, Abdullah Muzahid, Dario Suarez, Shanxiang Qi, Josep Torrellas, ISCA 2009.
38. A case for an interleaving constrained shared-memory multi-processor, Jie Yu, Satish Narayanasamy, ISCA 2009.
39. Designing and implementing malicious hardware, Samuel T. King, Joseph Tucek, Anthony Cozzie, Chris Grier, Weihang Jiang, and Yuanyuan Zhou, LEET 2008.
40. Raksha: a flexible information flow architecture for software security, Michael Dalton, Hari Kannan, Christos Kozyrakis, ISCA 2007.
41. New cache designs for thwarting software cache-based side channel attacks, Zhenghong Wang, Ruby B. Lee, ISCA 2007.
42. Dacota: Post-silicon validation of the memory subsystem in multi-core designs, DeOrio, A.; Wagner, I.; Bertacco, V., HPCA 2009.
43. FlexiTaint: A programmable accelerator for dynamic taint propagation, Venkataramani, G.; Doudalis, I.; Solihin, Y.; Prvulovic, M., HPCA 2008.
44. MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging, Venkataramani, G.; Roemer, B.; Solihin, Y.; Prvulovic, M., HPCA 2007.
45. Control flow obfuscation with information flow tracking, Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang, Pen-chung Yew, MICRO 2009.
46. Design and implementation of the AEGIS single-chip secure processor using physical random functions, Suh, G.E.; O'Donnell, C.W.; Ishan Sachdev; Srinivas Devadas, in ISCA 2005.
47. Efficient online validation with delta execution, Joseph Tucek, Weiwei Xiong, Yuanyuan Zhou, ASPLOS 2009.
48. Hardbound: architectural support for spatial safety of the C programming language, Joe Devietti, Colin Blundell, Milo M. K. Martin, Steve Zdancewic, ASPLOS 2008.
    
    Application-Specific Architectures
     
49. Understanding sources of inefficiency in general-purpose chips, Hameed et al., in ISCA 2010.
50. LINQits: big data on little clients, Chung et al., in ISCA 2013.
51. Navigating Big Data with High-Throughput, Energy-Efficient Data Partitioning, Wu et al., in ISCA 2013.
52. STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution, Atta et al., in ISCA 2013.
53. Convolution Engine: Balancing Efficiency and Flexibility in Specialized Computing, Qadeer et. al., in ISCA 2013.
54. Thin Servers with Smart Pipes: Designing SoC Accelerators for Memcached, Lim et. at., in ISCA 2013.
55. Neural Acceleration for General-Purpose Approximate Programs, Esmaeilzadeh et. al., in MICRO 2012.
56. Architecture Support for Disciplined Approximate Programming. Hadi Esmaeilzadeh (University of Washington), Adrian Sampson (University of Washington), Luis Ceze (University of Washington) and Doug Burger (Microsoft Research), ASPLOS 2012.
57. Hermes: an integrated CPU/GPU microarchitecture for IP routing, Yuhao Zhu, Yangdong Deng, Yubei Chen, DAC 2011.
58. AnySP: anytime anywhere anyway signal processing, Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner, ISCA 2009.
59. Rigel: an architecture and scalable programming interface for a 1000-core accelerator, John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel, ISCA 2009.
60. Anton, a special-purpose machine for molecular dynamics simulation, David E. Shaw and et al, ISCA 2007.
61. ParallAX: an architecture for real-time physics, Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman, ISCA 2007.
62. SODA: A Low-power Architecture For Software Radio, Yuan Lin; Hyunseok Lee; Woh, M.; Harel, Y.; Mahlke, S.; Mudge, T.; Chakrabarti, C.; Flautner, K., in ISCA 2006.
63. Processor acceleration through automated instruction set customization, Clark, N.; Hongtao Zhong; Mahlke, S., in MICRO 2003.
    
    Additional papers covered in lecture:
     
64. A Case for Unlimited Watchpoints. Joseph Greathouse (University of Michigan), Hongyi Xin (University of Michigan/SJTU), Yixin Luo (University of Michigan/SJTU) and Todd Austin (University of Michigan), ASPLOS 2012.
65. EFFEX: an embedded processor for computer vision based feature extraction, Jason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin, DAC 2011.
66. Fault-Based Attack of RSA Authentication, Andrea Pellegrini, Valeria Bertacco and Todd Austin, in the 2010 Design, Automation and Test in Europe Conference (DATE-2010), March 2010.
67. Razor: a low-power pipeline based on circuit-level timing speculation, Ernst, D.; Nam Sung Kim; Das, S.; Pant, S.; Rao, R.; Toan Pham; Ziesler, C.; Blaauw, D.; Austin, T.; Flautner, K.; Mudge, T., in MICRO 2003.
68. Energy optimization of subthreshold-voltage sensor network processors, Nazhandali, L.; Zhai, B.; Olson, A.; Reeves, A.; Minuth, M.; Helfand, R.; Sanjay Pant; Austin, T.; Blaauw, D., in ISCA 2005.
69. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Mukherjee, S.S.; Weaver, C.; Emer, J.; Reinhardt, S.K.; Austin, T., in MICRO 2003.
70. Ultra Low-Cost Defect Protection for Microprocessor Pipelines, Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin, in ASPLOS 2006.
71. Architectural implications of brick and mortar silicon manufacturing, Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd Austin, ISCA 2007.
72. Testudo: Heavyweight security analysis via statistical sampling, Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco, Seth Pettie, MICRO 2008.
73. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
    Kypros Constantinides, Onur Mutlu, Todd Austin, Valeria Bertacco, MICRO 2007.