EECS 573: Microarchitecture (Winter 2007)

Instructor:  Todd Austin, CSE 4637, austin@umich.edu

Office Hours:  Wednesday 1:30-2:30, Friday 11:00-12:00, or by appt.

Class Web Page:  http://www.eecs.umich.edu/courses/eecs573    (Visit often!)

Course Synopsis:  A graduate-level introduction to the foundations of efficient microprocessor designs. Problems involving instruction supply, data supply, and instruction processing, compile-time vs. run-time tradeoffs, and in-order vs. out-of-order execution. Special focus is placed on reliability, power-aware computing, and application-specific design. Case studies are taken from current microprocessors.

Text:  None, we will be reading papers available from the Web, they are listed below.

Course Schedule (tentative):

UMich Research Highlights

Project:  There will be one project beginning in week 3. Students may work in pairs or groups of three - of course, larger groups will be expected to produce more results. Students will conduct a research project that includes a quantitative evaluation of the proposed invention.  To help in this process, I make available for the class a microprocessor simulation system (SimpleScalar). Other projects are also possible with prior approval. Students will meeting with the professor to propose the project, meet during the semester for checkpoints, and finally produce a research report and present their findings in the final week of class.

Details of the project can be found here: http://www.eecs.umich.edu/courses/eecs573/PROJECTS.txt

The SimpleScalar sources and class benchmarks are available here:

  http://www.simplescalar.com/tools.html (use the 3v0d version)
  http://www.eecs.umich.edu/courses/eecs573/public/instruct-progs.tar.gz

Grading:    

Class Participation: 15%
Class Presentation: 15%
Exam: 30%
Project: 40%

Lectures:

1. Lecture 01 - Class presentation overview
2. Lecture 02 - Low-Power Robust Computing Tutorial
3. Lecture 03 - Application-Specific Design
4. Lecture 04 - Paper #55 presentation

Class forum:

    Here is the class forum, please add your comments about papers by 5pm the day before they are presented.  For more details see lecture 01.

 
Reading List:           

We will be reading the following papers. We will discuss them in the week specified in the table above, please have read the papers by the beginning of class.  NOTE: To view ACM and IEEE papers you must have an account with that institution OR you must access the papers from within the UMich.edu domain.

Power-Aware Computing

1. An ultra low power system architecture for sensor network applications, Hempstead, M.; Tripathi, N.; Mauro, P.; Gu-Yeon Wei; Brooks, D., in ISCA 2005.
2. Temperature-aware microarchitecture, Skadron, K.; Stan, M.R.; Huang, W.; Sivakumar Velusamy; Karthik Sankaranarayanan; Tarjan, D., in ISCA 2003.
3. "Flea-flicker" multipass pipelining: an alternative to the high-power out-of-order offense, Barnes, R.D.; Ryoo, S.; Hwu, W.W., in MICRO 2005.
4. Thermal Modeling, Characterization and Management of On-Chip Networks, Li Shang; Peh, L.; Kumar, A.; Jha, N.K., in MICRO 2004.
5. VSV: L2-miss-driven variable supply-voltage scaling for low power, Hai Li; Chen-Yong Cher; Vijaykumar, T.N.; Roy, K., in MICRO 2003.
6. Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction, Kumar, R.; Farkas, K.I.; Jouppi, N.P.; Ranganathan, P.; Tullsen, D.M., in MICRO 2003.
7. PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor, Taeho Kgil, Shaun D'Souza, Ali Saidi, Nathan Binkert, Ronald Dreslinski, Trevor Mudge, Steven Reinhardt, Krisztian Flautner, in ASPLOS 2006.
8. An ultra low-power processor for sensor networks, Virantha Ekanayake, Clinton Kelly, IV, Rajit Manohar, in ASPLOS 2004.
9. Performance, energy, and thermal considerations for SMT and CMP architectures, Yingmin Li; Skadron, K.; Brooks, D.; Zhigang Hu, in HPCA 2005.
10. On the limits of leakage power reduction in caches, Yan Meng; Sherwood, T.; Kastner, R., in HPCA 2005.
11. Exploiting prediction to reduce power on buses, Wen, V.; Whitney, M.; Patel, Y.; Kubiatowicz, J.D., in HPCA 2004.
12. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations, David Brooks, Vivek Tiwari, Margaret Martonosi, in ISCA 2000.
13. Very Low Power Pipelines using Significance Compression, R. Canal, A. Gonzalez, J. E. Smith, in MICRO-33.
14. Dynamic Zero Compression for Cache Energy Reduction, L. Villa, M. Zhang, K. Asanovic, in MICRO-33.
15. Drowsy Instruction Caches - Leakage Power Reduction using Dynamic Voltage Scaling, Nam Sung Kim, Krisztián Flautner, David Blaauw, and Trevor Mudge, in MICRO-35.

Resilient System Design

16. Design and evaluation of hybrid fault-detection systems, Reis, G.A. Chang, J. Vachharajani, N. Mukherjee, S.S. Rangan, R. August, D.I., in ISCA 2005.
17. Rescue: a microarchitecture for testability and defect tolerance, Schuchman, E.; Vijaykumar, T.N., in ISCA 2005.
18. Exploiting structural duplication for lifetime reliability enhancement, Srinivasan, J.; Adve, S.V.; Pradip Bose; Rivers, J.A., in ISCA 2005.
19. Techniques to reduce the soft error rate of a high-performance microprocessor, Weaver, C.; Emer, J.; Mukherjee, S.S.; Reinhardt, S.K., in ISCA 2004.
20. The case for lifetime reliability-aware microprocessors, Srinivasan, J.; Adve, S.V.; Bose, P.; Rivers, J.A., in ISCA 2004.
21. A mechanism for online diagnosis of hard faults in microprocessors, Bower, F.A.; Sorin, D.J.; Ozev, S., in MICRO 2005.
22. Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery, Armstrong, D.N.; Hyesoon Kim; Mutlu, O.; Patt, Y.N., in MICRO 2004.
23. AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants, Pin Zhou; Wei Liu; Long Fei; Shan Lu; Feng Qin; Yuanyuan Zhou; Midkiff, S.; Torrellas, J., in MICRO 2004.
24. Checkpoint processing and recovery: towards scalable large instruction window processors, Akkary, H.; Rajwar, R.; Srinivasan, S.T., in MICRO 2003.
25. A defect tolerant self-organizing nanoscale SIMD architecture, Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck, in ASPLOS 2006.
26. Fingerprinting: bounding soft-error detection latency and bandwidth, Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk, in ASPLOS 2004.
27. The soft error problem: an architectural perspective, Mukherjee, S.S.; Emer, J.; Reinhardt, S.K., in HPCA 2005.
28. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors, Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), in MICRO-35.
29. Non-Stalling Counterflow Architecture, Michael F. Miller, Kenneth J. Janik, and Shih-Lien Lu, in HPCA-4.

Application-Specific Architectures

30. SODA: A Low-power Architecture For Software Radio, Yuan Lin; Hyunseok Lee; Woh, M.; Harel, Y.; Mahlke, S.; Mudge, T.; Chakrabarti, C.; Flautner, K., in ISCA 2006.
31. A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching, Brodie, B.C.; Taylor, D.E.; Cytron, R.K., in ISCA 2006.
32. Architecture for protecting critical secrets in microprocessors, Lee, R.B.; Kwan, P.C.S.; McGregor, J.P.; Dwoskin, J.; Zhenghong Wang, in ISCA 2005.
33. Design and implementation of the AEGIS single-chip secure processor using physical random functions, Suh, G.E.; O'Donnell, C.W.; Ishan Sachdev; Srinivas Devadas, in ISCA 2005.
34. A high throughput string matching architecture for intrusion detection and prevention, Lin Tan; Sherwood, T., in ISCA 2005.
35. An architecture framework for transparent instruction set customization in embedded processors, Clark, N.; Blome, J.; Chu, M.; Mahlke, S.; Biles, S.; Flautner, K., in ISCA 2005.
36. A Hardware-Software Platform for Intrusion Prevention, Drinic, M.; Kirovski, D., in MICRO 2004.
37. RIFLE: An Architectural Framework for User-Centric Information-Flow Security, Vachharajani, N.; Bridges, M.J.; Chang, J.; Rangan, R.; Ottoni, G.; Blome, J.A.; Reis, G.A.; Vachharajani, M.; August, D.I., in MICRO 2004.
38. Processor acceleration through automated instruction set customization, Clark, N.; Hongtao Zhong; Mahlke, S., in MICRO 2003.
39. Introspective 3D chips, Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Tim Sherwood, in ASPLOS 2006.
40. Accelerator: using data parallelism to program GPUs for general-purpose uses, David Tarditi, Sidd Puri, Jose Oglesby, in ASPLOS 2006.
41. Secure program execution via dynamic information flow tracking, G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas, in ASPLOS 2004.
42. Mondrian memory protection, Emmett Witchel, Josh Cates, Krste Asanović, in ASPLOS 2002.
43. InfoShield: a security architecture for protecting information usage in memory, Shi, W.; Fryman, J.B.; Gu, G.; Lee, H.-H.S.; Zhang, Y.; Yang, J., in HPCA 2006.
44. Low-overhead interactive debugging via dynamic instrumentation with DISE, Corliss, M.L.; Lewis, E.C.; Roth, A, in HPCA 2005.

Special Assignment: System Case Studies

45. Microsoft XBox 360 Architecture

46. Sony Playstation 3 Architecture

47. Sun Niagara Architecture

48. AGEIA PhysX Architecture

49. iPod Shuffle Architecture

50. nVidia 8 Series Architecture

51. Pentium-M Architecture

Additional papers covered in lecture:

52. Razor: a low-power pipeline based on circuit-level timing speculation, Ernst, D.; Nam Sung Kim; Das, S.; Pant, S.; Rao, R.; Toan Pham; Ziesler, C.; Blaauw, D.; Austin, T.; Flautner, K.; Mudge, T., in MICRO 2003.
53. Energy optimization of subthreshold-voltage sensor network processors, Nazhandali, L.; Zhai, B.; Olson, A.; Reeves, A.; Minuth, M.; Helfand, R.; Sanjay Pant; Austin, T.; Blaauw, D., in ISCA 2005.
54. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Mukherjee, S.S.; Weaver, C.; Emer, J.; Reinhardt, S.K.; Austin, T., in MICRO 2003.
55. Ultra Low-Cost Defect Protection for Microprocessor Pipelines, Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin, in ASPLOS 2006.

Presentation Schedule: