Q: How do I make a TLF file for my memory? It is needed for outputting an SDF.

A: Cadence has a script to convert the Synopsys timing information in the .lib (or .syn) file
(generated by RapidCompiler) into a TLF. Do the following on your lib file:

syn2tlf .lib

Note, that this is the lib file that you spliced together from the cb25_memory_typ.lib and the
cell output information from RapidCompiler (e.g. rs6_1_typ.syn). See the FAQ on how to make
a Synopsys memory model.

---------------------------------------

Q: Is warning/error _fill_in_something_evil_sounding_ really bad?

A: All errors are bad. Usually Synopsys/Verilog will stop whatever it's doing.
Some warnings can be ignored. Usually, too few port connections (TFPC) and unknown values
during reset can be ignored. Other warnings depend on what is causing them. Understand the
warning before you say "it's ok".

---------------------------------------
Q: What does Synopsys warning/error AAA-NNN (AAA is letters, NNN is numbers) mean?

A: Check the error description section in the Synopsys Online Documentation (SOLD). It
is a hypertext PDF (acroread /nfs/ds/ecad5/synopsys-synth-2000.05/doc/online/top.pdf)
file so you can just go to:

man Pages and Error Messages -> Section (usually Error Messages) -> AAA-NNN

---------------------------------------
Q: How do I floorplan my blocks in SE?

A: There are two options.

To manually floorplan, you can place blocks by hand.
Click the "Sl" item by cells in the selection/visibility items in the main window. This
allows you to select cells. Click on the block you want to move, it will be highlighted.
Now select Edit->Move to place the block anyplace in the core rows. After you have placed
it, make sure to select Floorplan->Update Core Rows to get rid of the core rows where the
block was placed.

To have SE automatically place your blocks, you just select Place->Blocks. This might 
cause problems with power routing if the power pins (or other pins) are blocked since
we cannot route over memories or many sub-blocks. There should be a halo option when you
update the core rows to keep the standard cells away, but you have to watch out for
the macro blocks.


---------------------------------------
Q: My multicycle path or false path doesn't begin and end on a FF boundary, what
do I do?

A: Timing paths normally run from one sequential element to the next, or from inputs
(set_input_delay), or to outputs (set_output_delay). The trick is to use set_input_delay
and set_output_delay to "break" your timing arc. Do this:

set_input_delay 0.5*clk_period break_node
set_output_delay 0.5*clk_period break_node

Then you can use break_node in your false or multicycle path. Adjust the percentage of the
clock that you allocate to the path before and the path after accordingly, but make sure
that the total time is one clock period. The trick is to select break_node so that there
is only one timing path through it. Otherwise, if it is a result bus with multiple reconvergent
timing paths, it will falsely constrain other paths.

---------------------------------------
Q: Should I flatten a design?

A: By default, Synopsys doesn't optimize across module boundaries. To achieve this,
you can either flatten your design by:

set_flatten true

or

ungroup -all -flatten

or you can enable boundary optimization with the "-boundary_optimization" flag given
to the compile command

or you can do:

set_boundary_optimization subdesign

to allow it on a specific module.

---------------------------------------
Q:  After I synthesize, I get a bunch of warnings in Verilog that I have unconnected ports.
What should I do?

A: This is on all the DesignWare stuff. Instead of changing the ports, it just rips out the
unneeded stuff inside a module. Ungroup all the designware stuff before outputting your
Verilog with:

/* this will ungroup the designware stuff */
foreach ( des , find(design,"*")) {
	current_design des
  if ( find ( reference , "*DW*")) {
 	     foreach(inst , find(cell,"*")) {
 				      if ( get_attribute (inst DesignWare) == "true") {
					        echo inst
					        ungroup inst
				      }
  	    }   
	  }    
}    

---------------------------------------
Q: How do I import memories into SE?

A: After you make your .v, .syn, and gdsii views in RapidCompiler, you must
use "abstract" in Cadence to generate a LEF file to be used in SE.

1) run abstract -tech  when path points to the dir containing                                                               
tech.dpux                                                                                                                         
2) read in the gdsii - hierarchy is ok                                                                                            
2.5) put the top-level cell only into the Block bin. Operate only on                                                              
this cell - ignore the rest.                                                                                                      
3) read in the verilog - stubs are ok 
4) For pins: default settings should work but add:
(metal metal) (metal2 metal2) (metal3 metal3) (metal4 metal4) (metal5 metal5)
for "Map text..." in the Map tab. Also, you might need to adjust
boundary by 3-5um in "Adjust Boundary By..." in the Boundary tab.                                                                 
5) Leave extract settings at default.
6) Leave abstract settings at default.
7) Write out lef for the Block bin.

Then you can include the lef for your memory module just like a library or any
other macro block. Also read in the memory stub into 

* THERE ARE STILL A COUPLE ISSUES WITH THIS *
- THIS DOESN'T CREATE A SITE IN YOUR LEF
- THE TECH.DPUX DATABASE RESOLUTION IS DIFFERENT
- MUST REMOVE REDUNDANT LAYER INFO FROM LEF TO GET RID OF WARNINGS

---------------------------------------
Q: How can I write Verilog at home?

A: For those of you that want to work on some Verilog at home, you can use
Icarus Verilog on your Linux box. It is a Verilog compiler (not interpreter)
similar to VCS. It is sufficient for small to medium designs. It is available
at:

http://icarus.com/eda/verilog/index.html

To view the VCD file that is output, you can use GTKwave:

http://daggit.pagecreator.com/ver/wave/

The gEDA (GPL Electronic Design Automation) web page has some other possibly
useful tools:

http://www.geda.seul.org

---------------------------------------
Q: I need to have a register file where I can read from two registers and write to
a third. Is that possible to do without hand designing?

A: The quick answer is no, I don't know how to do this automatically except with
flip flops and muxes in Verilog.

To make register files, you want to use a small SRAM. As I'll mention several times
in the Synopsys discussion, you cannot synthesize memories, because:

1) it will take a long time
2) you end up with a bunch of flip flops which are space inefficient

So, for simple register files, we will have generators for the following SRAMS:

1) Synchronous single-port RAM. (1 Read/Write)
2) Asynchronous single-port RAM. (1 Read/Write)
2) Asynchronous two-port RAM. (2 Read/Write)
3) Asynchronous dual-port RAM. (1 Read, 1 Write)
4) Synchronous ROM. (I assume single-port only)

---------------------------------------
Q: What's a good Verilog reference?

A: If you want a book, get:

The Verilog Hardware Description Language
by Thomas & Moorby

If you just want on-line, the Bucknell Verilog Manual is at:

http://home.europa.com/~celiac/verilog-manual.html

---------------------------------------
Q: Should I use a DesignWare part?

A: Unless it's absolutely necessary, I recommend to NOT instantiate DW elements. This
makes your design dependent on the DW library. Synopsys is smart enough to match your
behavioral verilog to these DW elements on it's own...  So, unless you are synthesizing
many of the same unit (like the DSP group and multiplies) and want to reduce run-time by
instantiating them or you want to compare a certain type of unit (like Pat's multiplier
project) then don't use them...



---------------------------------------
Q: How do I set up the Passport libraries?

A: If you run csh or tcsh then just define these:

setenv LIBRA_HOME_DIR /afs/engin.umich.edu/caen/generic/mentor_lib-C.2/public/PASSPORT_0.18/2000.3
setenv LIBRA_PROD_DIR cb18/v1.0

and source:

$LIBRA_HOME_DIR/cb18.v1.0.cshrc

It's similar for the 0.25um library.

The documentation for the library (including RAM/ROM data sheets) is available at:

/nfs/ds/ecad4/PASSPORT_0.18/2000.3/cb18/v1.0/doc/main.pdf


---------------------------------------
Q: 	How do I make a Synopsys memory model?

A: I announced in class that I was still getting RapidCompiler to work
with Synopsys. Here is what you need to do:

output synopsys-model

This creates several files for the process corners called
cb18_tsmc_memory_min.syn (or max or typ)
rs6_1_min.syn (or max or typ)

the second name depends on what you specified with the getdefault command.

Before the final } in the cb18* file, add the contents of the rs6_1_min.syn
file. This adds your memory "cell" to the memory library. You need to have
different names for each memory config.

Then you can do:

read_lib combined_file.lib

to read your design at the beginning of your script. Also, make sure to add
cb18_tsmc_memory_min to your library path.

To make a more permanent library, you can do this:
write_lib cb18_tsmc_memory_typ -output test.db

Then load this file in your .synopsys_dc.setup.

---------------------------------------
Q: I was running sedsm manually and got the weird error message when running
FROUTE. Can you tell me how to fix it?

** LAYOUT-USER-100  ERROR **
Froute has found an error: Not enough memory. Please use bigger bootsize
or try setting Froute.Static.Memorysize to a value higher than 15
** CADENCE-USER-53  WARNING **
Input source will abort at next read due to limit of 1 PROBLEMs.

Unexpected error: database out of memory: DIAREN.DIRECLAIMALLARENAS (6.22)
 consider using bigger boot size

Please report this problem to applications support.
** CADENCE-USER-53  WARNING **
Input source will abort at next read due to limit of 1 PROBLEMs.



A: Run SE with the following command line:

 sedsm -m=300 &

 (or more memory than 300 if necessary!)

---------------------------------------
Q: How do I set up Synopsys to use the Avant! library?

A: Make a .synopsys_dc.setup file in your home directory with this info. You
can change to the 0.25 process and add your own memory library.

designer = "Christopher Weaver"
company  = "University Of Michigan"
PROJECTDIR      = "/tmp"
VERILOGDIR      = "/tmp/verilog"
AVANTI          = "/afs/engin.umich.edu/caen/generic/mentor_lib-C.2/public/PASSPORT_0.18/2000.3/cb18/v1.0/synopsys/1999.05/"
SYNOPSYS = get_unix_variable("SYNOPSYS")

/*Avanti typical  */
STDCELL_LIB = AVANTI + "models/tsmc/cb18os120_tsmc_typ.db"
IOGEN_LIB       = AVANTI + "models/tsmc/cb18io220_tsmc_typ.db"
STACKEDIOGEN_LIB = AVANTI + "models/tsmc/cb18sio220_tsmc_typ.db"
MEMORY_LIB       = AVANTI + "models/tsmc/cb18_tsmc_memory_typ.db"
earch_path = search_path + VERILOGDIR
synthetic_library = { dw_foundation.sldb }

link_library = { "*", STDCELL_LIB, IOGEN_LIB, STACKEDIOGEN_LIB, MEMORY_LIB,
dw_foundation.sldb }
target_library = { STDCELL_LIB }
symbol_library  = {AVANTI + "icons/cb18io220.sdb",  AVANTI
+"icons/cb18os120.sdb", AVANTI + "icons/cb18sio220.sdb"}

verilogout_no_tri = true
hdlin_translate_off_skip_text = true
hdlin_use_cin = true

---------------------------------------
Q: How do I do timing driven design (TDD)?

A: There are two ways. A short way (recommended) and the long way (better,
but more difficult).

The short way (without doing Pearl timing analysis):
1) In Synopsys, synthesize your design. Then output an SDF file that
covers your timing paths:
  write_constraints -cover_design -format sdf -output .sdf

2) Import lef, gcf and verilog in sedsm as before. Then import the sdf you 
wrote out above with: File->Import->SDF...                                                                                       
In cell placement, click on "Timing Driven Placement" (can also have
"Pin Placement" selected).
In WROUTE, click on "Timing Driven Routing". Keep "Global and Final
Route" and "Auto Search and Repair" selected.      

The long way (using Pearl timing analysis):
Check out Chapter 6 of openbook (SE version). Pay particular 
attention to the SDF flow. The basics of this are:

1) In Synopsys, synthesize your design. Then output an SDF file that
covers your timing paths:
	write_constraints -cover_design -format sdf -output .sdf
And then output a constraints script:
	write_script .scr
Make sure that you didn't synthesize a clock network!

2) Using the Pearl timing analyzer, convert the Synopsys constraint script
to a GCF constraint file:
	run pearl
	> read_dc_script .scr
	> write_gcf .gcf
	> gcfcheck (just to be sure it worked)

3) Use the Pearl timing analyzer w/ SDF from synopsys, Synopsys constraints
(translated to GCF), and the Passport environment GCF file 
(PASSPORT_0.25/2000.4/cb25/v2.1/cds/GCF/*) to verify timing on your design.
This will go something like this (details in the chapter):

>ReadGCFTimingLibraries .gcf
>ReadVerilog .v
>TopLevelCell 
>ReadSDF .sdf
>Clock -cycle_time    
>CheckTiming
(optional) > ShowPossibility [from] [to]
> IdealClocks yes
> TimingVerify
(optional) > ShowPossibility [from] [to]

Make sure it passes... (or the manual says within 5%). 

4) Then in SE (you actually should use seultra for this)

Edit your se.ini file to select the TDD flow:
set variable wroute.timing.driven true;
set v timing.placement.extraction.model qp_global_opt;
set v qplace.timing.mode true;

Then do make your design:

	- import the LEF like normal
	- import the environment GCF file (shown above)
	- import your verilog
	- import the SDF output by synopsys
	- import the GCF constraint file made by pearl

5) Then follow the remaining commands similar to the tutorial, but it will do
timing driven placement and routing.

I haven't run through this yet, but this is the general timing driven design
flow. I will post additions if there are problems.


---------------------------------------
Q: What is the minimum I should do?

A:


A minimal flow would be the tutorial with special routing for the clock net:

After you place your design, run Place->CTGen. Edit the constraints file to specify
your clock pin, frequency, skew, etc. Then generate a buffered clock tree by
pressing OK.  (this will insert buffers and then make sure there's no overlap in 
the placement). You can then view the results to see if your clock tree meets 
your constraints.

After you have placed the clock tree, you route it as a special net by selecting
Route->ClockRoute. Specify the same root IO pin and skew that you did before.

It will then call WROUTE to route just the clock net and report the skew at the end
of the command:

#---{clockRoute : ===========================================}
#---{clockRoute : ============ ClockRoute Result ============}
#---{clockRoute : ===========================================}
#---{clockRoute : Tree 1: Clock tree root: PIN CLK}
#---{clockRoute :          M1 wirelength: 454 [7%] -> 454 [7%] (100%).}
#---{clockRoute :          M2 wirelength: 3246 [53%] -> 3246 [53%] (100%).}
#---{clockRoute :          M3 wirelength: 2404 [39%] -> 2404 [39%] (100%).}
#---{clockRoute :          M4 wirelength: 31 [.50207%] -> 31 [.50207%] (100%).}
#---{clockRoute :   Wirelength: 6135 -> 6135 (100%).}
#---{clockRoute :   Min delay :743 ps -> 743 ps (100%)}
#---{clockRoute :   Max delay :764 ps -> 764 ps (100%)}
#---{clockRoute :   Max skew  :21 ps -> 21 ps (100%)}
...


Then, continue the rest of the tutorial as normal.

Your design, however, has extra cells due to the clock tree now. So you need to do
a File->Export->Verilog when you output an SDF file for backannotation.


---------------------------------------

Q: I get errors in my SE layout? What do I do?

A: Debug them.

Always rerun Verify->Geometry and Verify->Connectivity after you route
(especially with WROUTE). It doesn't seem to update usually.

Edit->Find Info will display an errors in a useful way... (zoom in,
point and click, etc)

You can then manually edit wires using Edit->Wire.
I've been able to correct loops (a connectivity violation)
and you can route a wire manually (for example, if there's a power
hookup problem).

You can also add blockages with Edit->Blockage->Add to prevent routing in
certain areas.


---------------------------------------
Q: How do I run my Verilog simulations with the Avant! library?

A:
Here is how you should include the libraries for verilog:

verilog_sst temp.v -y (path)/PASSPORT_0.25/2000.4/cb25/v2.1/verilog/cb25os163/zero +libext+.v
-v (path)/PASSPORT_0.25/2000.4/cb25/v2.1/verilog/cb25os163/zero/mtb_verilog.v

If you don't do this, you get an error message like this:

Error!    Number of user defined primitives exceeds
          maximum of 255. 5 system defined primitives used
					          for this design
										[Verilog-NOUDP]
										1 error

---------------------------------------
Q: How do I view my Verilog output in Signalscan?

A:

In your Verilog, add the following lines:

initial begin
  $shm_open("/tmp/debug.shm");
  $shm_probe(st, "AS");
end

where st is the module you want to start recording at. 
There is also an option that can specify the maximum module depth you want
to record in your hierarchy. This is handy
when designs (and output files) get really big. Then, simulate with verilog
as your verilog executable. Now, you can view the output with:

signalscan /tmp/debug.shm

---------------------------------------
Q: What are all the different libraries (.db files) in the Avant! library?

A:

Here's a summary of what the different libraries are:

"Optimum Silicon" (OS) Standard Cells : cb25os163
In line I/Os 2.5/2.5V 3.3V tolerant : cb25io123
In line I/Os 2.5/3.3V 5V tolerant : cb25io223
Staggered I/Os 2.5/3.3V 5V tolerant : cb25sio223
In line PCI I/Os 2.5/3.3V 5V tolerant : cb25pc223
Staggered PCI I/Os 2.5/3.3V 5V tolerant : cb25spc223