Synthesis

DC shell scripts

• set up environment (library, wire model, etc.)

 
search_path = ...  /* where to look for files when using the line command */
target_library = ...  /* the library the compile command uses for mapping */
link_library = ... /* designs referenced in your design */
symbol_library = .../* the pretty symbols used in graphical design_analyzer */
set_wire_load <library_wire_model> -mode segmented
 
• read .v files in (analyze, elaborate)

 
/* RTL modules */
module_list = { module1, module2, module3 }

/* Analyze and elaborate */
foreach (file_name, module_list)
{
 analyze -work CORE -format verilog file_name + ".v"
 if (dc_shell_status != 1) {
  sh echo 'Analyze Error:' file_name
  quit
 }
 elaborate -update -work CORE -arch "verilog" file_name
}
/* Makes sure all needed designs are in memory */
link
 

• specify clocks (create_clock, set_clock_skew)

This creates a clock with 3% clock skew and a 50% duty cycle. The waveform option gives the high portion of the clock. The set_dont_touch_network command prevents synthesis from inserting buffers.
 
clk_period = 50
clk_skew = 0.03 * clk_period     /* 3% of clock period as skew */
clk_name = "clk_c"
create_clock -name "gclk_c" -period clk_period -waveform {0 25} clk_name
set_attribute clk_name is_clock true -type boolean -quiet
set_clock_skew -uncertainty clk_skew -propagated clk_name
set_dont_touch_network find(port, "clk_c")
 
• add constraints (set_input_delay, set_output_delay, set_load, set_max_area)

The first constraints are for 80% of the clock period. This is a default constraint that I use. Any time it is not a good constraint, simply over-ride it in the script file with a less  strict constraint. This is a useful tactic when the inputs/outputs of a module are changing a lot. If you forget to add a constraint, it will flag it in your reports as a violation.
 
/* Generic delay - make it very strict */
set_input_delay 0.8 * clk_period -clock gclk_c { all_inputs() - clk_name }
set_output_delay 0.8 * clk_period -clock gclk_c all_outputs()

/* inputs */
mem = 0.68 * clk_period
set_input_delay mem -clock gclk_c  find(port, "if_mem_in_b*")

/* outputs */
adp = 0.75 * clk_period
set_output_delay  adp -clock gclk_c  find(port, if_mem_addr_b*)
set_load 3.5 find(port,if_mem_addr_b*)
 

• remove false paths (set_false_path)

 
/* starting/stopping points must be a port/pin */
/* You can make one manually using the set_input_delay/set_output_delay command */
set_false_path -from portA -to portB
 
• synthesize (compile)

 
compile -map_effort medium
• generate reports (setup/hold violations, area, power, etc.)

 
 report_constraints -all_violators -verbose > report.constraints
report_timing -path end -delay max -max_paths 200 -nworst 2 > report.paths
report_timing -path full -delay max -max_paths 5 -nworst 2 > report.full_paths
report_area > report.area
report_reference > report.refs
 
• generate SDF file

 
write_timing -output  "out.sdf"  -load_delay cell -format sdf -context verilog

Hierarchy

• Longest synthesis run should be an hour or two. Divide the design appropriately.
• Compile sub-blocks then use "set_dont_touch <block>" to prevent top level compile from recompiling them.
• Make sure to include timing constraints for the sub-block (make a timing budget!)
• Make sure to use an appropriate directory structure. This can prevent a lot of hassle.
• Use revision control!

Special Nets (clocks)

Simple method is to hand instantiate buffers & dont_touch the network. This requires hand partitioning the clock nets so that the loads are approximately balanced. Newer P&R tools can add buffers after placement is done so that more accurate RC information can be used.