Laboratory 4 (team) -- Hardware encryptor/decryptor

Overview

Max circuit

Before designing your circuit, make sure you understand the max circuit covered in lecture. Here is a schematic drawing of the datapath for the max circuit. The following are the Verilog files for that circuit; you may use any of them in your circuit:

• top.v contains the top-level module for the circuit. It instantiates other components (which may in turn instantiate other components).
• control.v contains the control unit for the circuit. It is implemented as a finite-state machine. Here is the truth table for this control unit.
• clocks.v generates the clock signal for the rest of the circuit. Use the clock signal for the registers, memory, and finite-state machine in your circuit. clocks.v can be configured to produce various speed clock signals. You need not understand how clocks.v produces the different clock speeds, but you do need to modify clocks.v to choose a clock speed for your circuit. At the bottom of the file, you will see an always block that chooses between various speed clocks. Uncomment exactly one of these lines (by deleting the initial //). You can pick various free-running clocks (ranging from 1.5 Hz to 1.6 MHz); you can also pick a manual clock, controlled by ~KEY[1]. Pick a slow clock or the manual clock when debugging. After you're done debugging, try using a faster clock.
• reset_toggle.v generates the reset signal. reset is initialized to 1 when the circuit is downloaded to the FPGA, and changes (between 0 and 1) each time ~KEY[0] is pushed and released. The value of reset is displayed on LED_GREEN[8].
• equal16.v contains a combinational block of logic that tests whether the input is equal to 16.
• greater.v contains a combinational block of logic that tests whether the first input is greater than the second.
• plus1.v contains a combinational block of logic that computes the input + 1.
• ram.v is a memory component. The memory is comprised of 256 words, with each word being 8 bits. You need not understand how this module is implemented, though you should understand how it is used.
• register.v is an 8-bit register.
• tristate.v is an 8-bit tri-state driver.

Rot13

rot13 translates each character of a message by "rotating" it 13 places in the alphabet. Thus, the letter a becomes n, b becomes o, c becomes p, and so on. Toward the end of the alphabet, the letters "wrap around" back to the beginning, so n becomes a, o becomes b, and so on. For example, the message "hello" would be encrypted as "uryyb". Note that you can reverse a rot13 transformation by re-applying rot13, so rot13 can be used to decrypt a message as well as to encrypt it.

Encryptor/decryptor circuit

You are to build a circuit that transforms a message using rot13. Assume the message is composed solely of lower-case letters, represented by their standard ASCII values (e.g., "a" is represented by 97, "b" by 98, and so on). The message is stored as an array in memory, starting at address 0. The end of the message is terminated by an entry with the value 0 (this is the same convention used by C to store strings).

When your circuit starts, it should transform all characters in memory, starting from address 0 and proceeding up to (but not including) the termination entry. Upon reset, your circuit should start back at address 0 and transform the message in memory again. Use ~KEY[0] to change the reset signal, just as in Lab 3.

Your circuit should be structured similarly to the max circuit. top.v should contain your module top, and control.v should contain your control unit, implemented as a finite-state machine. You will need other modules to complete your datapath; each of these modules should be contained in a separate file. Your circuit should display the current value of the 8-bit bus on HEX1 and HEX0.

Pre-lab assignment

Your team's pre-lab assignment is to design a datapath and control unit for the rot13 circuit and to write the Verilog for all components in your circuit (including the control unit). You should meet as a team at least once or twice before the lab to design a solution and review each other's parts. You should arrive at your lab section with a complete solution that you believe should work. The lab time is meant for testing, debugging, and demonstrating your circuit.

Here are some common errors to look out for:

• Misordered or missing signals in module instantiations (especially the control unit).
• Incorrect number of bits in the control unit's state register or parameter values.
• Forgetting to declare a variable as multiple bits.

In-lab demonstration

Demonstrate your hardware encryptor/decryptor to a lab instructor. Use Quartus' In-System Memory Content Editor to write a message to memory and verify the results of the transformation, then verify that the transformation is reversed when you reset the circuit and re-process the message.

To write data to memory with the memory editor, edit the memory contents shown on the main window, then right-click on this window and select Write Data to In-System Memory (screenshot). When downloading data to FPGA memory, you should stop the the circuit to prevent it from also accesssing FPGA memory. To do this, make sure the reset signal is on before downloading data to FPGA memory and leave the reset signal on until the download is done. Resetting the circuit in this way will also clear all registers (at the next positive clock edge), which will have the desired effect of re-starting the encryption/decryption algorithm at address 0.

After you've demonstrated your circuit to a lab instructor, one member of your team should submit the final version of the Verilog files used in your datapath. You need not submit Verilog files that are identical to the files in the max circuit.