Heterostructure FETs with Lattice-Matched or Strained Channels

InP based lattice-matched and strained devices have been studied theoretically and experimentally. The effect of strain has been demonstrated using various FET designs, such as HEMTs and HIGFETs. Both n- and p-channel devices were explored. Accomplishments made in this area are listed below:

• Evolution of Technology and Impact on HFET Technology

• Evolution of III-V Technology

• FET Gate Development

• Mobility improvement from 11500 cm^2/V-sec to 13900 cm^2/V-sec at room temperature using 12 % excess Indium in InGaAs channels.

• Measurement of field-velocity characteristics in strained inGaAs/InAlAs heterostructures. Velocity improvement of 7.4 % and 14.8 % was demonstrated with 7 % and 12 % excess Indium respectively.

• Establishment of device design approach for strained InGaAs HEMTs. Optimum designs can be achieved using the results of this approach on the influence of strain, doping and channel thickness on sheet carrier density, strained channel carrier occupation, ``parasitic-MESFET'' conduction, etc.

• First demonstration of double-channel InGaAs/InAlAs HEMTs and output conductance improvement using the double versus single designs. Record fMAX's of 66 GHz were achieved using 1um long gates. fT=140 GHz was obtained with 0.25 um gates.

• Understanding of low frequency noise characteristics and impact of strain. The results demonstrated that a compromise had to be made between high-gain (large excess In % and low-noise (low excess In % ).

• A thorough study of the low-frequency dispersion characteristics of InGaAs/InAlAs HEMTs revealed smallest transconductance and output resistance dispersion for slight excess in (7 % ) in the channel. The dispersion is smaller than in MESFETs and is identified to originate from the channel region under the gate.

• First reliability studies of InGaAs/InAlAs HEMTs revealed DC and high frequency degradation. Changes in the channel buffer interface and layers manifested by additional trapping seem to be responsible for this.

• Demonstration of submicron bilayer technology and application to the fabrication of 0.1 um InGaAs/InAlAs HEMTs. Record fT's and fMAX's in the range of 200 GHz to 240 GHz were achieved.

• First realization of p-channel GaInP/InGaAs/GaAs HEMTs. Channel mobility enhancement from 117 cm cm^2/Vs to 340 cm^2/Vs and transconductance enhancement up to 47 mS/mm was demonstrated by incorporating 10 % In in the channel. N- and p-channel HIGFETs were also realized for the first time using GaInP/InGaAs/GaAs.

• Demonstration of n-channel GaInP/GaAs HEMTs with gm=163mS/mm, fT=17.8 GHz, fMAX=23 GHz for 1 um long gates.

• Demonstration of absence of threshold voltage shift and current collapse in cryogenic operation of GaInP/GaAs HEMTs. Superiority over AlGaAs/GaAs and InGaAs/InAlAs was shown.

• Investigations of i-layer and step-doped designs for HEMTs showed that better threshold voltage uniformity could be obtained in recessed devices, together with improved linearity and reduced low-frequency noise in such designs.

• HEMT breakdown analysis using a two-dimensional approach. A screening effect of transverse from longitudinal electric field was identified. Double channel designs were analyzed to explain their breakdown advantages over single channel devices.

• Demonstration of E/D mode HIGFET technology with best recorded standard deviations of threshold voltage and state-of-the-art speed characteristics.

• Demonstration of enhancement in mobility (8330 cm^2/Vs to 12890 cm^2/Vs), transconductance (289mS/mm to 428mS/mm) and K-values of InAlAs/In(x)Ga(1-x)As HIGFETs by increasing the In composition x from 53 % to 65 % .

• Development of novel refractory metal WSi submicron gate technology. Unlike traditional technologies, this approach employs lift-off rather than RIE for gate definition. Reduced gate leakage is manifested due to channel protection from the implants by the T-shape of the gate.

• Introduction of p-buffer in submicron n-channel HIGFETs and demonstration of reduced short channel effects.

• Realization of state-of-the-art InP-based HEMT characteristics using self-aligned gates for improved fMAX characteristics and demonstration of fMAX=310 GHz using this technology with 0.1 um long-gates.

• Analysis of subthreshold conduction in InAlAs/InGaAs HIGFETs and demonstration of more pronounced effects in strained devices related to higher carrier injection to the buffer and presence of a deep trap (E(DT)=0.34 +- 0.01-eV, N(DT)=2.4e16 cm^-3)

• Demonstration of correlation between transconductance dispersion and low-frequency noise by generation-recombination in GaInP/GaAs and AlGaAs/GaAs HEMTs. Evaluation of trap presence during high temperature operation of GaInP/GaAs devices but absence of such effects at low temperature.

• Demonstration of threshold voltage shift and orientation effects in InAlAs/InGaAs HIGFETs due to piezoelectric charges induced by the WSi refractory gate metallization.

• Report of the highest fT obtained by MOVPE grown InAlAs/InGaAs HEMTs. A value of 180 GHz has been reached using 0.1 um long-gates.

• Realization of strained, multichannel p-doped InAlAs/InGaAs heterostructure FETs. Demonstration of the advantages of dual-channel lightly doped designs over single channel heavily doped devices; strain has no significant effect in the latter, due to Fermi-level overlapping with higher effective mass bands.

• Study of kink effect in p-doped InAlAs/InGaAs FET and proposal of impact ionization in channel as possible mechanism.

• Demonstration of increased implant activity in p-channel InAlAs/In(x)Ga(1-x)As HIGFETs by C+Ar co-implantation; the implant activity was 70 % for C+Ar vs. 4 % for C. Reduced access resistance and improved gm demonstrated for C+Ar implanted HIGFETs.

• Study of gate-feeders in InAlAs/InGaAs HIGFETs and demonstration of significant reduction of sidegate effects by use of airbridge gate-feeders.

• First demonstration of E/D InAlAs/InGaAs HIGFETs on the same wafer using selective ion-implantation. High uniformity (sigmaV(th)=8mV for E-mode and sigmaV(th)>=12mV for D-mode) was demonstrated and high DC gain (20) E/D inverters were fabricated.

• Implementation of photoconductive probe techniques for the demonstration of 25 psec switching times in E/D InAlAs/InGaAs inverters.

• Introduction of cold measurement techniques for the identification of parasitics in submicron InP-based HEMTs. Evaluation of intrinsic Y-parameters and equivalent circuit elements after stripping-off parasitics. Demonstration of significantly reduced error in Ri and Tau evaluation using the above technique and capability of accurate model extraction for W- and D-band HEMTs.

• Study of the impact of recess on InAlAs/InGaAs HEMT characteristics and demonstration of improved fMAX /fT ratios and reduced microwave noise by higher gate aspect (Lg / Dg ) ratios.

• Demonstration of self-aligned offset-gate-technology and gate lengths down to 0.07 um for InAlAs/InGaAs HEMTs. The technology employs a trilayer HI/LO/He-beam technique. fMAX/ fT improvement up to 2.7 was demonstrated by offsetting the gate.

• Demonstration of high open channel current (1A/mm), higher voltage gain (21) and improved fMAX (310 GHz vs. 280 GHz) using DHEMT rather than SHEMT InAlAs/InGaAs designs.

• Development of a 2D ensemble Monte-Carlo simulation technique for HEMTs and explanation of the lower fT in DH-InAlAs/InGaAs HEMTs by increased interface roughness at the bottom interface and reduced channel electron velocity.

• Demonstration of fMAX=350 GHz and open channel current density of 1.2A/mm using sub-0.2 um offset self-aligned Gamma gates in DH-InAlAs/InGaAs HEMTs.

• Demonstration of Quasi-ID InAlAs/InGaAs HEMTs with shallow gratings for reduced gate leakage and high full channel current. Unlike deep grating devices, shallow grating Quasi-D HEMTs demonstrated current drive as high as that of devices without grating.

• Demonstration of improved fMAX (270 GHz vs. 230 GHz) using Quasi-1D (0.4 um pitch) InAlAs/InGaAs HEMTs instead of conventional designs and asttribution of improvement to increased Gm/Gds and Cgs/Cgd.

• Application of 2D-Ensemble Monte-Carlo simulation to submicron InP-based HEMT and development of a delay time analysis. Demonstration of the importance of velocity modulation by the gate voltage in determining the device delay.

• Demonstration of: (i) considerably longer transit than delay time in the source and drain fringing region of InAlAs/InGaAs HEMTs, (ii) minimum contribution of source region to total device delay and (iii) prime (65 % ) contribution of gate to total delay; the remaining delay is due to the drain region.

• Evaluation of bias dependence of delay times in InAlAs/InGaAs HEMTs and role of each region on these characteristics.

• Comparison of Y-factor and noise power approaches for noise characterization of FETs and demonstration of better repeatability for the latter.

• Demonstration of increased parasitic drain noise in HEMTs vs. MESFETs due to the higher transconductance of the former.

• Demonstration of higher intrinsic drain noise in HEMTs than MESFETs due to the higher effective doping and shorter gate lengths of the former.

• Demonstration of in-house MOCVD grown InAlAs/InGaAs 1 um-long gate HEMTs with record characteristics of fT=60 GHz, fMAX=120 GHz.

Technical Developments

Review of Group Activities