Self-Aligned Technology for GaAs and InP-based Heterojunction Bipolar Transistors (HBTs)

Graduate Students : Don Sawdai, Apostolos Samelis
Professor D. Pavlidis, Hidenori Shimawaki*
U.S.Army Research Office DAAL03-92-G-0109, NEC Inc. and Bell Northern Research

This work has focused on the development of state-of-the-art technologies for the fabrication of high-speed Heterojunction Bipolar Transistors (HBTs) for the InP/InGaAs, AlGaAs/GaAs and GaInP/GaAs material systems. The emitter-base separation is reduced to 1000A in order to minimize parasitic base access resistance. This significantly improves the HBT high-speed performance and allows a closer look at the device physics. Reactive Ion Etching (RIE) techniques are employed to obtain a vertical side- wall profile, and then wet chemical etching is used to expose the base for contacting, create the overhang required for self-alignment, and to remove plasma damage encountered during the RIE step. RIE conditions based on BCl(3) and CH(4) plasmas have been characterized for the etching of GaAs, AlGaAs, InP, InGaAs, and GaInP.

The GaInP/GaAs material system has also been extensively studied in order to develop reliable wet etch chemistries and dry etch plasma etching conditions for control of the self- alignment etching step. Improved conduction and valence band offsets, thermal junction coefficients and surface recombination make this material system an attractive candidate for HBT devices, but material quality, crystal disorder and heterointerface intermixing during growth all contribute to difficulties for the etching of the emitter HBT layer. Successful processes have been developed to overcome these problems, and good device characteristics for self-aligned structures have been demonstrated.

Design optimization of InP/InGaAs HBTs is performed using a newly designed mask set which includes base contacts self-aligned to two parallel edges of the emitters, small intrinsic devices, minimal ohmic contact geometries, airbridge interconnects, multiple mesa isolation, removal of all intrinsic junction capacitances and trench isolation to reduce parasitics caused by air bridge pads. A technology is being developed for the removal of the extrinsic InGaAs HBT base by ion-milling or wet process. This technology aims at minimum parasitics such as reduction of base collector capacitance and thus improvement of high frequency performance of InP/InGaAs HBTs.

Current Research Programs: HBTs

Current Research Programs

Review of Group Activities