ECE Students: EECS 427 - VLSI Design I AMD/Michigan Student Design Contest

The annual Advanced Micro Devices (AMD) / Michigan Student Design Contest was held among the students of EECS 427: VLSI Design I.

First Place, Best Project ($1,500 Prize), 2010
"Design and Implementation of a 4k Embedded 3T DRAM"

ECE Team Members: Anuj Chandawalla, Durgesh Deshpande, Maksym Kloka (EE undergraduate), Neel Natekar and Sonal Verma (all, except for Kloka, are EE graduate students) demonstrated 3-transistor embedded dynamic random access memory (eDRAM) can be integrated with the microprocessor. The group was able to increase the data retention time of the memory to 659 microseconds to reduce the power needed for data refresh. Resulting 4Kbit memory is capable of 850 MHz operations for a high-performance microprocessor.

Second Place, Most Innovative Project ($500 Prize), 2010
"Low Power Sub-Threshold 400mV SRAM"

ECE Team Members: Haidar Aizat, Kai Boon Ee, Karan Jain, Aswin Srinivasa Rao and Indusekar Reddy demonstrated 8-transistor static random access memory (SRAM) can operate at a 400 mV supply voltage for extremely low power operations. SRAM is designed specifically for low-power applications such as wireless sensor nodes (WSN). The group focused on the SRAM because it is the most power consuming module in WSNs, and in this design targeted the sub-threshold application.

Third Place, Best Engineering ($500 Prize), 2010
"Power and Speed Optimized 16-bit Processor with Out-of-Order Instruction Execution"

ECE Team Members: Adam Brackmann, Saurabh Chauhan, Zhen Liu, Abhishek Roy and Ahsen Tahir implemented out-of-order dataflow execution (OOE) to improve performance of a microprocessor. Processor incorporates sparse-tree arithmetic logic unit (ALU) for high speed, and clock gating and power gating for low power.

Second Place ($2,500 Prize), 2008
"FreeFood: A 1GHz High-Performance 16-bit DSP with SIMD Multimedia Extensions"

ECE Team Members: Gautam Bhatnager, Brent Climans (BSE EE), Andrea Pellegrini, Bo Xiao (MSE EE), and Dan Zhang (BSE EE) attempted to provide uncompromising performance for video decoding and other complex multimedia operations while maintaining reasonable power efficiency in a novel 16-bit DSP. With creative and carefully balanced pipelining, FreeFood achieved a 427 record 1.05GHz clock rate and can sustain a maximum thoughput of 4200 MIPS consuming only 348mW. Features included a dedicated multiply-accumulate, 64-bit SIMD operations, and stream buffers.

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