July/August 2007 issue of
IEEE Design &
Test is devoted to Computer-Aided Design for Emerging Technologies. At
the heart of these emerging technologies are nanoscale circuits, which are
subject to a greater variety of potentially damaging influences and, at the
same time, are increasingly difficult to test because of their
non-deterministic behavior. Prof.
John Hayes, Prof.
Igor Markov, and graduate
student Smita Krishnaswamy describe a first-of-a-kind technique to test
non-deterministic parameters of such nanocircuits in their article,
"Tracking Uncertainty with Probabilistic Logic Circuit Testing."
In conventional circuit test, only permanent manufacturing faults are
considered. However, nanocircuits can suffer from more subtle faults that
overexpose them to environmental noise and several types of radiation.
Therefore, manufacturers will need to test chips for transient output errors
caused by these phenomena. Furthermore, high-altitude and high-radiation
environments require online testing to continually check that a circuit
functions reliably. This alters the goal of testing nanocircuits from
detecting specific defects to accurately estimating error probability.
Krishnaswamy et al provide a stochastic matrix-based framework for the
representation and analysis of circuits with probabilistic faults. For the
first time in the literature they propose scenarios for testing standard
circuit benchmarks with respect to stochastic phenomena and statistically
predicting their behavior.
Note: The complete article can be found on