Valeria Bertacco Awarded CAREER Grant for Project: Correctness Constrained Execution for Processor Designs   Bookmark and Share

Prof. Valeria Bertacco, Assistant Professor in the Department of Electrical Engineering and Computer Science, has been awarded an NSF CAREER grant for the project, “Correctness Constrained Execution for Processor Designs.”

The project seeks to integrate software and hardware innovations to ensure a processor works correctly, even with design flaws. The team will first create two modes of processor operation: one high–performing and a second, simple, low-performance mode that has been verified at design time and can, therefore, be trusted to perform correctly. Using a new piece of hardware called a state checker, functions will be allowed to run in high-performance mode until the system meets with an unverified state, at which time the sequence will be referred to the failsafe low-performance mode. Bertacco's goal is to provide processor designs that are functionally correct under every execution scenario.

According to Bertacco, two thirds of private sector hardware design funding is devoted to verification, while the majority of college course offerings are devoted to design. Bertacco contends that colleges haven’t done enough to address the imbalance: “Among students, the verification process is often perceived as lacking a creative aspect, in contrast with project design. However, this perception can be corrected by approaches which require creativity in devising and designing fall-back mechanisms that are an integral part of the system, and that blur the line separating design from verification.” Bertacco is in the process of creating an undergraduate-level design verification course, and plans to enhance current graduate-level offerings in verification. The graduate courses will be expanded to include the most recent techniques in semi-formal verification, design-for-verification, post-silicon correction mechanisms and quantitative metric evaluation.

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Valeria Bertacco is a member of the Advanced Computer Architecture Laboratory in the Division of Computer Science and Engineering. She conducts research in the functional verification of hardware designs, focusing mainly in the creation of novel techniques and verification methodologies that enable the formal and semi-formal verification of industrial scale designs.

The CAREER grant is one of NSF’s most prestigious awards, conferred for “the early career-development activities of those teacher-scholars who most effectively integrate research and education within the context of the mission of their organization.”