U-M Team Wins Clock Network Synthesis Contest at ACM ISPD 2010   Bookmark and Share


Dongjin Lee and Myunchul Kim

Michigan students Dongjin Lee and Myungchul Kim, graduate students in electrical engineering, won first place in the 2010 Clock Network Synthesis Contest at the ACM International Symposium on Physical Design of Integrated Circuits, held March 14 - 17 in San Francisco, CA, beating teams from Hong Kong and Taiwan who took second and third places, respectively. Lee and Kim were advised by Prof. Igor Markov on the project. This victory is the second in a row for Lee and Markov, who shared first prize with two teams from Taiwan universities in the 2009 contest.

The focus of both the 2010 and 2009 contests was to design algorithms and software for computer-aided design of "clock networks." A clock network distributes clock signals to sequential elements of a large integrated circuit; clock networs are of interest because they are becoming a limiting factor in the performance of leading-edge chips.

Viewing the 2009 contest as a warm-up, the organizers from IBM Research joined forces with experts from Intel Research and made this year's contest more challenging. In particular, clock signals had to arrive within a 7.5 picosecond window, even though the chips were subject to process and voltage variation. In addition to several such constraints, the main objective of the 2010 contest was to minimize total power usage, which would allow the chip to run longer on battery. Contest benchmarks were based on microprocessor designs from Intel and IBM.

This contest included several rounds of competition, during which the field was narrowed from 20 to 10 teams. That field was further narrowed to four finalists (Taiwan, Hong Kong, Michigan, and Purdue) and software programs produced by each team were evaluated by IBM researchers against hidden benchmarks using a lengthy numerical simulation on a cluster of 80 servers.

Of special note, the Michigan team produced circuits that were four times more power-efficient than those of the team that took second place. The image to the right is one example of a highly-efficient clock circuit submitted at one stage of the competition. Click on the image or this link for more detail regarding the circuit. The contest and results summary document (pdf) provides additional detail.

Read More:

EE Times, IBM Benchmarks Prod Microprocessor Designers


Posted: April 2, 2010