The image below shows a microprocessor layout with four routing obstacles (which correspond to certain modules inside the microprocessor). Small black crosses show the locations of sequential elements (latches and flip-flops) outside the obstacles. These are the "sinks" of the clock distribution network. The source (clock-signal generator) is in the lower left corner. Green lines show the wires of the clock network, emanating from the source to the sinks (the first wire reaches the center of the chip, and then starts branching). Blue rectangles overlaid on wires indicate the locations and sizes of repeaters (inverters) that reinforce the clock signal as it travels through narrow wires. Diagonal wires are implemented by combinations of vertical and horizontal segments.

To satisfy the contest constraints, the time traveled by the signal from the source to each sink had to be almost the same, and the results were compared by the total capacitance of wires and buffers -- the smaller then better.

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