2010 AMD/Michigan Student Design Contest for EECS 427

Three teams split $2,500 in cash prizes in the 5th annual Advanced Micro Devices (AMD) / Michigan Student Design Contest, held this past term (Fall 2010) for students in EECS 427: VLSI Design I. Each design achieved lower power consumption at the same time that they improved performance.

Present to judge the projects from AMD was Juang-Ying Chueh (PhD EE 2006), senior design engineer and AMD University Campus Team University of Michigan team lead. "I am very impressed," stated Dr. Chueh, "with how much students could accomplish and learn within one semester on VLSI design: analytical approaches, magnificent ideas, and dedicated effort." In addition to supporting the contest, AMD regularly provides simulation pool high end CPU computers for specialized research.

Prof. Zhengya Zhang taught the course, while Wei-Hsiang Ma provided significant support to the students as the graduate student instructor.  

First Place - Best Project (prize: $1,500)
Design and Implementation of a 4k Embedded 3T DRAM

First place team First Place chip

L-R: Anuj Chandawalla, Sonal Verma, Durgesh Deshpande, Neel Natekar, Maksym Kloka


The designers for the winning project were: Anuj Chandawalla, Durgesh Deshpande, Maksym Kloka, Neel Natekar, and Sonal Verma. They are all majoring in electrical engineering, and except for Maksym Kloka, a senior undergraduate student, they are master's students.

This group demonstrated a 3-transistor embedded dynamic random access memory (eDRAM) that can be integrated with the microprocessor. Describing the impetus for their design, Sonal Verma, stated, "Increasing demand for low power portable devices alongside expectations of higher operating frequencies to handle multithreaded operations has forced IC technology to embrace on-chip memory modules. While in the past peripheral DRAM modules enabled memory chip designers to utilize specialized processes like deep trench capacitors, unique doping profiles, and specialized material properties, embedded memory forces the designer to deal with the same fabrication steps allocated to standard silicon processes."

The group was able to increase the data retention time of the memory to 659 microseconds to reduce the power that is need for data refresh. The resulting 4Kbit memory is capable of 850 MHz operations for a high-performance microprocessor.

Second Place - Most Innovative Project (prize: $500)
Low Power Sub-Threshold 400mV SRAM

2nd place team chip
Karan Jain, Kaiboon, Indu Reddy, Aswin Rao [Aizat Haider not present]  

The designers for the most innovative project were: Haidar Aizat, Kai Boon Ee, Karan Jain, Aswin Srinivasa Rao, and Indusekar Reddy.

This group demonstrated an 8-transistor static random access memory (SRAM) that can operate at a 400 mV supply voltage for extremely low power operations. The SRAM is designed specifically for low-power applications such as wireless sensor nodes (WSN). The group focused on the SRAM because it is the most power consuming module in WSNs, and in this design targeted the sub-threshold application.

The SRAM had a Static Noise Margin (SNM) of 128mV and a write margin of 155mV which is considered very good for sub-threshold applications. They integrated the SRAM into a 16 bit RISC processor powered at 1.2V and demonstated the capability of the system for low power systems. They would turn their attention to sleep mode in the SRAM for future innovations. View the group's poster for more information about this design.

Third Place - Best Engineering (prize: $500)
Power and Speed Optimized 16-bit Processor with Out-of-Order Instruction Execution

3rd Place Team
Saurabh Chauhan, Adam Brackmann, Zhen Liu, Abhishek Roy
[Ahsen Tahir not present]

The designers for the best engineering project were: Saurabh Chauhan, Adam Brackmann, Zhen Liu, Abhishek Roy, and Ahsen Tahir.

This group implemented an out-of-order dataflow execution (OOE) to improve the performance of a microprocessor. The processor incorporates a sparse-tree arithmetic logic unit (ALU) for high speed, and clock gating and power gating for low power.

Zhen Liu said that the contest provided the team with great motivation to think more and create more, and that the final project exceeded the basic requirements asked for with good performance. Saurabh Chauhan agreed that the contest provided a valuable impetus to the class, and added that the project fosters a team spirit that is of great value.

More Information - 2009 Winning Project and EECS 427 Video

2009 1st Place Chip

The winning project from Fall 2009 was entitled, "Self-testing GALS Systems on Chip with 2X2 Mesh NOC," by Chandrika Dattathri, Mohammad Aiman Khan, Shashank Mahajan, and Ritesh Parikh. Students from this project are featured in a video that provides a brief introduction to the course:

427 Video

Posted: January 5, 2011 by
Catharine June
EECS/ECE Communications Coordinator or 734-936-2965