Electrical Engineering and Computer Science

2010 AMD/Michigan Student Design Contest for EECS 627   Bookmark and Share

With projects for energy efficient wireless sensor nodes and a "Wolverine" timing error detector to enable very low supply voltage in processors, two teams earned prizes in the 5th annual AMD (Advanced Micro Devices) / Michigan Student Design Contest, held this past term for students in the advanced VLSI Design class. First place and $2,000 went to Abhishek Roy, Kunal Garg, Phil Knag, Zhen Liu, and Praveen Kalish for their project, "Low-power Variation-tolerant compressive sensing ASIC for wireless sensor nodes," while second place and $1,500 went to Inyong Kwon, Josh Kim, Myungbo Kim, and Yen-po Chen for their project, "Wolverine: Modified D Flip-Flop for Timing Error Detection in Pipe-Line Processors."

Each year, students in EECS 627: VLSI Design II have the opportunity to earn cash prizes for their designs thanks to the sponsorship of AMD, as do students in the earlier course, EECS 427: VLSI Design I. [see results for EECS 427: VLSI Design I, Fall 2010] Judging the projects this year from AMD were Dr. Spencer Gold and Dr. Juang-Ying Chueh, both U-M alumni, as well as the graduate student instructors for the class, Greg Chen and David Fick. The course was taught by Prof. Dennis Sylvester.

First Place
Low-power Variation-tolerant compressive sensing ASIC for wireless sensor node

1st place team chip

L-R: Zhen Liu, Phil Knag, Kunal Garg, Abhishek Roy, Praveen Kalish

 

The designers for the winning project were Zhen Liu, Phil Knag, Kunal Garg, Abhishek Roy, and Praveen Kalish, all graduate students majoring in electrical engineering.

Describing the project, the group stated, "We designed an ASIC which implements the ISTA algorithm to reconstruct sparse data (compressive sensing). This ASIC was intended for wireless sensor nodes and so the most critical requirement was to be as energy efficient as possible with a reasonable computing time. Our ASIC used canary circuits to track PVT variations and minimize the SRAM power. Dual edge triggered flip flops were used in the design to reduce energy consumed by the clock tree, which makes up 40-50% of total core energy. We also used DVFS using look-up table to reduce core voltage. In addition, to optimize for long idle periods, we used power gating to reduce core leakage. The compressive sensing ASIC has applications in signal reconstruction, image processing and feature detection in wireless sensor nodes. The chip was designed in 0.13μm cmos technology. Operating the chip at run, wait and deep sleep modes, we were able to make our design energy efficient."

Second Place
Wolverine: Modified D Flip-Flop for Timing Error Detection in Pipe-Line Processors

2nd place teamInyong Kwon, Josh Kim, Myungbo Kim, Yen-po Chen

2nd place chip

The designers for the Wolverine project were Inyong Kwon, Josh Kim, Myungbo Kim, and Yen-po Chen, all graduate students majoring in electrical engineering.

The students described the project, "Dynamic voltage and frequency scaling (DVFS) have been widely used in the design of power efficient processors. However, in order to obtain maximum power savings in such system, it is necessary to operate with very low supply voltage. To find such an operating point that eliminates all safety margins, it is critical to monitor the system with a timing error detector. Today, optimization tools are capable of generating well-balanced pipeline stages causing the number of critical stages to increase, thus demanding a cheaper timing error detector. In this paper, we propose a new timing error detector, called wolverine, which only requires 8 more transistors than a traditional D Flip-Flop (DFF). Wolverine allows in-situ monitoring with significantly less area and power overhead compared to traditional error detectors. Simulation results in standard 0.13μm process prove Wolverine to be effective in error detection."


Posted: May 16, 2011 by
Catharine June
EECS/ECE Communications Coordinator
cmsj@umich.edu or 734-936-2965