Associate Professor Valeria Bertacco and CSE alumnus Ilya Wagner have co-authored a new book entitled "Post-Silicon and Runtime Verification for Modern Processors," which has been published by Springer.
The book surveys the state of the art and evolving directions in post-silicon and runtime verification. It provides an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. It thoroughly presents several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and could help accomplish the ultimate goal of complete correctness guarantees for microprocessor-based computation.
The book also addresses an area of hardware verification that is growing both in industry and academia, covers hardware patching and error avoidance, and discusses multi-core processors with test generation and response evaluation. The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle.
Prof. Bertacco is a member of the Advanced Computer Architecture Laboratory (ACAL) at CSE.
Her research interests are in the functional correctness of hardware designs, focusing in the creation of novel techniques to guarantee correctness in face of functional errors and temporary and permanent transistor failures. Her present research is centered on the development of new algorithms for hybrid verification and post-silicon validation and debug.
Dr. Wagner is a Research Scientist in the Platform Validation Engineering group at Intel, where he works on the design of advanced post-silicon validation and silicon debug architecture for future generations of Intel microprocessors. He is also involved in creating tools for platform developers that utilize the validation features and speed up the debug process. In the past, Dr. Wagner worked at Intel's Oregon Microarchitecture Lab, researching techniques to enable survivability in future systems on chip, sponsored by a post-doctoral fellowship from the National Science Foundation and Computing Research Association.
Posted: March 24, 2011