7th Annual AMD/Michigan Student Design Contest
Thanks to the sponsorship of Advanced Micro Devices, Inc., students in the Fall 2012 EECS 427 (VLSI Design I) class competed against their classmates for cash prizes in the 7th Annual AMD/Michigan Student Design Contest.
This course has a reputation for being very intense, yet continues to attract many students because of the excellent background it provides students in VLSI circuit design. This year, more than 60 students took this team project-oriented, major design experience course.
Ultra-Low Leakage Subthreshold 8T SRAM with Speed Compensation
Abhijith Kini Gokuldas, Naveen Bharathwaj Akesh, Aditya Maskeri, Nischit Bharadwaj, Akanksha Jain
Akanksha Jain, Nischit Bharadwaj, Naveen Bharathwaj Akesh, Abhijith Kini Gokuldas, Aditya Maskeri
Low power SRAM design is important in modern day processors as it consumes a high percentage of total power (majority of which is through leakage) and occupies considerable area compared to other components in the processor. With technology scaling, the number of transistors per unit area increases making energy efficiency a critical factor in battery-operated applications like Wireless Sensor Networks. Subthreshold computing has become a desirable candidate for such applications due to their minimized energy per operation. But the primary impediment to their adoption in modern processors is the increase in process variations. Our main motivation for this project was to design and implement some of the low power circuit optimization techniques taught in EECS427 while having less area overhead and optimal delay.
In this project, we designed a low leakage subthreshold 8T SRAM cell using High VT (HVT) devices in IBM 0.13μm CMOS process. Techniques like Bit-Line boosting (for fast write operation), Reverse Body Biasing (for low leakage), Sense Amplifier Redundancy (for fast read operation), Bit-interleaving (for overcoming soft errors) and custom write logic (to overcome half-select problem) are employed in our SRAM to improve its performance at subthreshold. The improved 8T SRAM has a bit-cell area of 6.2196 μm2 with a leakage power of 2.56 fW while operating at 0.3V (~5900x improvement over 6T standard cell at 0.3V). The SRAM has a Static Noise Margin (SNM) of 80mV for hold and 125mV for write. The array efficiency of the SRAM is 76.34 % and the maximum frequency of operation is 4 MHz. The average energy consumption of SRAM is 85.95 fJ per bit. As future work, we plan to make the SRAM more robust towards process variations.
Low Power 3T Embedded DRAM
Adrian Montero, Hang Li, Lili Wang, and Shihan Huang
Bottom (left to right): Adrian Montero and Hang Li
Top (left to right): Shihan Huang, Lili Wang, Yaoyu Tao (GSI), Supreet Jeloka (GSI), Professor Zhang
The goal of this project is to design a low power and high speed eDRAM using IBM 0.13 μm CMOS technology
High-level embedded DRAM architecture
Our 3T bit-cell design uses low power PFETs to implement write and read transistors, and low-VT PFETs to implement storage transistor. It achieves a write delay of 223 ps, a read delay of 404 ps, and retention time of 110 µs with a 3σ confidence interval under a 0.9 V supply voltage and a -0.5V word-line voltage. The area of the proposed bit cell is 1.66 × 1.07 μm2. Additionally, a sense amplifier design is discussed that supports a typical sense margin of 11.5 mV and a reading window of 350 ps at nominal conditions. The implemented eDRAM can achieve a read access time of 1.15 ns + 3ns (APR row decoder delay), and a write access time of 1.05 ns + 3 ns. Finally, an area efficiency of 42.81% has been achieved.
Third Place (tie)
An Ultra Low Leakage 10T SRAM with Speed Compensation Scheme
Wanyeong Jung, Michael Laskey, Zhao Xu, Myungjoon Choi, Donguk Yang
Wanyeong Jung, Michael Laskey, Donguk Yang, Myungjoon Choi
Sensors are becoming increasingly popular in areas like biomedicine, transportation, energy monitoring and infrastructure. However, to help increase this popularity and make sensors possible for new applications like being embedded into living tissue, a longer lifetime is required. To increase this lifetime, it is imperative to design ultra-low power circuits. Since most sensor nodes are clocked at a heavy-duty cycle of almost 99%, the chip is kept in standby mode for the majority of the time. To reduce power in standby mode, the CPU is fully power gated. The only section that can’t be power gated though is the volatile memory. Thus, designing a SRAM that minimizes leakage power is essential for increasing the lifespan of sensor motes. We propose a 10T SRAM that is designed to reduce standby leakage power.
Layout of the whole system, IO pads, and layout of 1 bit cell
We built a 10T SRAM with high voltage transistors (HVT) cross-coupled inverters, 4T readout circuit, reverse body biasing, VSS lifting and power gating methods. Bit line voltage is boosted to compensate slowed write speed. As a result, this system achieves low-power standby mode while sustaining high operational speed.
Third Place (tie)
A Low-Power, Low-Voltage ALU and Register File for Energy-constrained Applications
Kyusok Lee, Adam Mendrela, Jihong Min, Madin Kim, Yu-Ju Lin
Adam Mendrela, Madin Kim, Jihong Min, Kyuseok Lee, Yu-Ju Lin
We implemented a low-power and low-voltage Arithmetic Logic Unit (ALU) and Register File (RF) for an energy-constrained microprocessor.
Many applications such as portable or implantable systems allow for the computing power to be compromised in order to achieve low-power solutions performance. In near-sub-threshold operation region, transistor gates have greatly reduced dynamic and static power consumption, at an even higher rate than the clock speed. In order to balance critical path delay and energy efficiency, we utilized LVT's in stacking-only logic gates. Also, we designed a sense-amplifier-based amplifier and our RF achieved very high process variation resistance and incredibly short setup time. We achieved a very large improvement in power consumption of the processor compared to the baseline design at 1.2V and 15% improvement over the baseline design at 0.5V.
April 1, 2013
EECS/ECE Communications Coordinator
email@example.com or 734-936-2965
Instructor: Prof. Zhengya Zhang
2011 Contest - EECS 427
2010 Contest - EECS 427
2010 Contest - EECS 627
2008 Contest - EECS 427/627