6th Annual AMD/Michigan Student Design Contest
Students in the Fall 2011 EECS 427 (VLSI Design I) class competed against their classmates for cash prizes in the 6th Annual AMD/Michigan Student Design Contest. The winning designs were a Lower Power 8T SRAM Design, and a Lower Power 3T Embedded DRAM Design. This contest is held in both EECS 427 and EECS 627 (VLSI Design II) classes.
Thanks to this year's sponsorship by AMD, the students will share prize money in the amount of $3K.
Lower Power 8T SRAM Design
Matthew Land, Supreet Jeloka, Vandana Bansal, Arjun Rajpuhorit, Yue Ma (pictured above, LR)
As technology is scaling down, the leakage power has become the dominating factor in the total power consumption. In battery-operated applications, such as cellular phones and PDAs, the leakage power is now the deciding factor for determining the battery's life. The motivation for this 8T SRAM design was to implement low power techniques in such a way that they minimized the impact on area and performance while giving a substantial reduction of leakage current for on-chip memories in standby.
We designed a low leakage 4kb 8T SRAM in 0.13µm CMOS process. The design implemented a 0.3V reduced swing to retain the state while in low power standby mode. A dual-VDD architecture has been used to provide voltage to the bit-cell and float the periphery circuit while in standby. This implementation has shown a simulated leakage of 51.7fW for one bitcell and associated periphery in typical corners.
This corresponds to a 20,000X reduction in leakage as compared to the 6T implementation without reduction techniques.
Lower Power 3T Embedded DRAM Design
Shuanghong Sun, QiHao Wang, JiaLun Lin, YiXin Luo, ZheTao Zhang (pictured below, LR)
Our group's final project was to design low-power computer memory cells. We presented and characterized our proposed 3 transistor (3T) embedded DRAM with the ultimate goal of lowering energy consumption.
Compared to conventional DRAM designs, our design has fewer transistors but still results in longer retention time. Through extensive Monte Carlo simulations and coupling design techniques, it was possible for our proposed 3T embedded DRAM cells to achieve an average retention time of 1.25ms. Using our techniques to reduce of power, the dynamic power in a one-bit-cell results in 323nW and static power is 312fW. We used a single ended, positive feedback sense amplifier for read operation. The average read delay from Monte Carlo simulations is 913ps and the average write delay is 145ps. It is possible to achieve a 1GHz frequency. For future work, we aim to reducing the power overhead in the row decoder and controller.
February 28, 2012
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Lower Power 8T SRAM and Lower Power 3T Embedded DRAM are Winning Designs
Here are the results for the 6th Annual AMD/Michigan Student Design Contest for EECS 427: VLSI Design I.
Instructor: Prof. David Blaauw
Graduate Student Instructor: Zhiyoong Foo