The book entitled, "VLSI Physical Design: From Graph Partitioning to Timing Closure," co-authored by Professor Igor Markov, his recent Ph.D. advisee Jin Hu, Andrew B. Kahng, and Jens Lienig, has recently been translated into Chinese. The English and Chinese versions of the book are available on Amazon.com for purchase.
The book introduces and evaluates algorithms used during physical design to produce a geometric chip layout from an abstract circuit design, and presents the essential and fundamental algorithms used within each physical design stage. Its focus is on algorithms for digital ICs, such as system partitioning for field-programmable gate arrays (FPGAs) or clock network synthesis for application-specific integrated circuits (ASICs). Similar design techniques can be applied to other implementation contexts such as multi-chip modules (MCMs) and printed circuit boards (PCBs).
Prof. Ralph H.J.M. Otten of Technical University of Eindhoven states, “A clear sign of when a field matures is the availability of a widely accepted textbook. Finally, there is a well-balanced textbook that introduces the key components of a layout synthesis flow with sufficient depth and an eye for the context in which they are used. It lucidly presents what any maker of chip design tools should have as a core foundation.”
Prof. Markov has co-authored five books and more than 180 refereed publications, some of which have been honored by best-paper awards. He is the recipient of a DAC Fellowship, an ACM SIGDA Outstanding New Faculty award, an ACM SIGDA Technical Leadership Award, an NSF CAREER award, an IBM Partnership Award, a Synplicity Inc. Faculty award, a Microsoft A. Richard Newton Breakthrough Research Award, and the inaugural IEEE CEDA Early Career Award.
Posted: November 3, 2014