World’s Largest Processor Announced; Perfect for Big Data – and Other Applications

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Apr. 1, 2015 -- Computer architecture researchers in the Computer Science and Engineering division of the EECS Department at the University of Michigan have announced a new paradigm in the evolution of computer development: the world’s largest processor chip, designed for big data.

The chip, code-named "Mammoth," is a massively parallel processor that relies on aggressive voltage supply scaling to deliver zeta flops of performance with miniscule power consumption. In particular, by relying on near-zero-voltage circuits, Mammoth delivers data center scale performance while drawing about as much power as a household hair dryer.

Addressing the notorious issue of prohibitively high power densities (which result in under utilization of processor resources, a phenomenon known as Dark Silicon), Mammoth brings Dennard scaling back on track, ushering in a new "Era of Big Silicon."

A New Direction in Processor Development

Research scientist and project leader Prob Knot characterized the development of the extra-large processing unit with respect to widely-held expectations. "We are aware that the introduction of Mammoth runs counter to the recent trend in chip design, which has typically been focused on creating extremely small, often power-constrained processors," said Knot. "Mammoth reverses this trend. People are going to have to get used to it."

A Mammoth slab.

According to Knot, the Mammoth multicore architecture is scalable to billions of cores, rivaling the number of neurons in a human brain, and the mega-chip’s true potential will not be realized until software can be developed to fully optimize its operation. "In its current implementation, the first-generation Mammoth processor that we will unveil today can easily provide the data processing capability of a medium-sized data center," said Knot.

Big Footprint - Big Opportunities

The tradeoff for Mammoth’s jaw-dropping processing capabilities is its unusually large footprint. Mammoth chips will be fabricated in reinforced "slabs" that are measured in meters, not millimeters, and can potentially scale to the size of a city block.

"Some might expect this size to deter adoption," said Knot, "but Mammoth holds great promise as an essential building block in the next-generation Internet of Things."

For example, Knot notes that Mammoth slabs could be used as construction panels for smart buildings and structures. "Wherever there is a need to seamlessly embed massive and inexpensive amounts of computing into our living environments, Mammoth makes perfect sense," said the researcher. "A single Mammoth-powered dormitory on North Campus would provide the computational power required to support all research conducted at the College of Engineering."

While initially impressed, faculty in the department have appeared reluctant to fully embrace Knot’s vision. "Although I applaud the idea of a really big chip," said one, "I wouldn't want to live or work in it."

Another commented, "I could get on board with this, but quite frankly I think if it catches on we’re going to run out of problems to solve – big data or not. What am I going to do then?"

Knot plans to unveil the Mammoth prototype at noon today in Tishman Hall, the atrium of the Bob and Betty Beyster Building – if it fits.

Posted: April 1, 2015