For their groundbreaking research in power-efficient computing, faculty and former students of the department received the 2017 ACM SIGARCH (Special Interest Group on Computer Architecture) and IEEE-CS TCCA (Technical Committee on Computer Architecture) ISCA (International Symposium on Computer Architecture) Influential Paper Award.
This award recognizes the paper published 15 years ago, in this case 2002, in ISCA Proceedings that has had the most impact on the field (in terms of research, development, products or ideas) during the intervening years.
The paper, Drowsy Caches: Simple Techniques for Reducing Leakage Power, was originally published in the ACM/IEEE Proceedings of the 20th Annual International Symposium on Computer Architecture, May 2002, by Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, and Trevor Mudge. At the time, the research was conducted by faculty and students in the Advanced Computer Architecture Laboratory (now the Computer Engineering Laboratory), which is part of the Computer Science and Engineering division, in collaboration with faculty and students in the division of Electrical and Computer Engineering.
The paper was written when current leakage in transistors was becoming a major concern, especially in the design of high end processor chips. Transistors were becoming so small, the electric current would continue to flow between transistors even when the transistor switch was turned off.
"The current literally would jump across the transistor," explained Blaauw.
The problem was particularly acute in the relatively large on-chip caches, or memories, of high-end processors.
"The idea in the paper, and subsequent papers and patents," said Mudge, "was to intelligently put parts of a computer's cache into a low power 'drowsy' mode - thereby saving energy."
For some of the caches, the voltage would be cut to a level where the data residing in those caches were still retained, but could no longer be accessed. "In that state they consume much less power," said Blaauw, "and then when you want to access the data, you raise the voltage."
The authors stated in the paper that, "with simple architectural techniques, about 80%-90% of cache lines can be maintained in a drowsy state without affecting performance by more than 1%." In a 0.07 μm CMOS process, this would result in a reduction in total energy consumed in the caches by 50%-75%.
The concept, though simple, was powerful in its ability to reduce total power consumption. Since 2002, the technique has been adopted by major chip manufacturers, and has continued to be exploited in subsequent research by the authors themselves.
The SIGARCH ISCA Influential Paper Award will be conferred at the 44th International Symposium on Computer Architecture (ISCA), held in Toronto, CA June 24-28, 2017. ISCA is the premier forum for new ideas and research results in computer architecture.
About the authors
Prof. David Blaauw focuses on ultra-low-power and adaptive VLSI design, including millimeter-scale sensor nodes, and low power data servers.
Dr. Krisztián Flautner (BSE MSE PHD CSE, '96 '98 '01) is General Manager, Internet of Things Business at ARM. He was advised by Prof. Mudge.
Prof. Nam Sung Kim (PHD CSE '04) is an associate professor of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign. His current research focuses on hardware systems. He was advised by Prof. Mudge, and his dissertation further explored the topic of drowsy caches and related issues.
Dr. Steven Martin (MSE PHD EE '01 '05) is currently R&D Manager at Avago Technologies.
Trevor Mudge, Bredt Family Professor of Engineering, focuses on computer systems design, low power computing, parallel processing, computer-aided design, and impact of technology.