Converging Architecture, Implementation, and Software Development through Parallelized Simulators
Wednesday, April 21, 2010|
12:00pm - 1:00pm
3725 Beyster Bldg.
About the Event
In order to accurately simulate parallel computers quickly, simulators themselves must be parallelized. However, simulators have been traditionally difficult to parallelize due to the tight dependencies and frequent communication that characterize standard partitioning. In this talk, I will describe a novel simulator architecture that enables the efficient parallelization of accurate computer system simulators running on a hybrid multicore+FPGA host system. We are developing a prototype that accurately models memory ordering regardless of the simulated memory model, data speculation, and aggressive branch prediction (with power and reliability modeling being added) while supporting the x86 ISA, booting unmodified Linux
and running unmodified applications. It runs at roughly 10MIPS per host core in accurate mode, and significantly faster in less accurate modes. In addition, the description of such a simulator can be mechanically synthesized into an implementation, significantly reducing the effort required to translate an architectural specification into RTL.
Derek Chiou is an assistant professor at the University of Texas at Austin. His research areas are high performance computer simulation, computer architecture, parallel computing, Internet router architecture, and network processors. For five years before going to UT, Dr. Chiou was a system architect at Avici Systems, a manufacturer of terabit core routers. Dr. Chiou received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT. His research is supported by a DOE Career award, an NSF CAREER award, NSF and SRC awards as well as donations from Intel, IBM, Xilinx, Freescale, Altera, and VMWare.
Contact: Lauri Johnson-Rafalski
Event Sponsor: Satish Narayanasamy
Open to: Public