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Defense Event

Adaptive Architectures for Robust and Efficient Computing

Shantanu Gupta


 
Monday, April 25, 2011
10:30am - 12:30pm
3725 Beyster Bldg.

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About the Event

NOTE: Defense actual start time is 10:45 a.m. Semiconductor technology scaling has long been a source of dramatic gains in our computing capabilities. However, as we test the physical limits of silicon feature size, serious reliability and computational efficiency challenges confront us. The supply voltage levels have practically stagnated, resulting in increasing power densities and operating temperatures. Given that most semiconductor wearout mechanisms are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Further, the rise in power density is also limiting the number of resources that can be kept active on chip simultaneously, motivating the need for energy-efficient computing. In this landscape of technological challenges, incremental architectural improvements to existing designs are likely insufficient, motivating a need to rethink the architectural fabric from the ground up. Towards this end, this thesis presents adaptive architecture and compiler solutions that can effectively tackle reliability, performance and energy-efficiency demands expected in future microprocessors. For the reliability challenge, we present StageNet, a highly reconfigurable multicore architecture that is designed as a network of pipeline stages, rather than isolated cores. The interconnection flexibility in StageNet allows it to adaptively route around defective pieces of a processor, and deliver graceful performance degradation in the face of failures. We further complement the fault isolation ability of StageNet with an adaptive testing framework that significantly reduces the overhead of in-field fault detection. As a second contribution, we build upon the interconnection flexibility of StageNet to develop a unified performance-reliability solution. This subsequent design, named CoreGenesis, relies on a set of microarchitectural innovations and compiler hints to merge processor cores for a higher single-thread performance. This enables customization of processing ability (narrow or wide-issue pipelines) to the dynamic workload requirements. In the third and final work of this thesis, we investigate the sources of computational inefficiency in general purpose processors, and propose a configurable compute engine for substantial energy savings. The insight here is to cut down on the redundant instruction fetch, decode and register file access energy by optimizing the execution of recurring instruction sequences.

Additional Information

Sponsor(s): Scott Mahlke

Open to: Public