EECS
EECS


Defense Event

Probabilistic Methods for Analyzing and Simulating Digital Circuits

Chien-Chih Yu


 
Friday, June 15, 2012
10:30am - 12:30pm
1690 BBB

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About the Event

Due to the rapid progress of the CMOS manufacturing technologies, integrated circuit (ICs) can now contain billions of transistors. This great complexity has forced engineers to rely on electronic design automation (EDA) software tools to design, verify and test new ICs. In addition, modern ICs are sensitive to manufacturing process variations and soft errors caused by environmental disturbances. Hence, there is an increasing need for probabilistic characterizations of IC behavior that can be easily incorporated into EDA tools, and can be used in situations where traditional deterministic approaches are ineffective. The goal of this dissertation is to develop ways to significantly improve the quality of the probabilistic analysis techniques required for EDA. To achieve this goal, we present a methodology for sampling input signals that improves accuracy and runtime; we also introduce a trigonometry-based technique for efficiently analyzing soft errors by mapping signal probabilities into angles. Finally, we propose a reliability estimation method for calculating signal and error probability distributions in sequential circuits. The contributions of this dissertation identify features of probabilistic, error-inducing phenomena that can lead to significant improvements in circuit quality. They also reduce the computational overhead for probabilistic calculations which are essential for many EDA tasks.

Additional Information

Sponsor(s): John P. Hayes

Open to: Public