About the Event
Low power techniques for continuous-time bandpass ∆Σ modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW.
Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators.