Defense Event

Compact Power Amplifiers Using Circuit Level and Spatial Power Combining Techniques

Waleed Alomar

 
Wednesday, December 04, 2013
10:00am - 12:00pm
3316 EECS - Haddad Conference Room

 

About the Event

High power, high efficiency, and compact size are important performance measures of power amplifiers used in transmitters for civilian as well military communications and radars. It is difficult to achieve all the above performance measures at the same time. Several new high power, high efficiency, and compact size power amplifier designs are introduced in this dissertation. A new circuit level power combining technique, which is capable of achieving high power levels while maintaining high efficiency and small size, is introduced here. It consists of cascoded class-E power amplifiers based on a high voltage / high power (HiVP) design technique. Several power amplifiers are designed and implemented using microstrip circuits and packaged LDMOS devices at VHF. Design equations for HiVP class-E power amplifier are also derived. To the best of the author’s knowledge, this is the first demonstration of a class-E HiVP power amplifier. Subsequently, a compact millimeter wave spatial power combining technique using serially fed antenna arrays is introduced in this dissertation. Several power amplifiers are incorporated with antennas in a serially fed array in order to combine their output power in free space. Design techniques for broadband serially fed antenna arrays employing new lossless negative group delay (NGD) circuits are reported. Several lossless NGD circuits are designed at Ka-band, X-band, and S-band frequencies. NGD is generated by employing the resonance behavior of microstrip-fed quasi-Yagi antennas, microstrip patch antennas and amplifiers with matching circuits.

Additional Information

Event Sponsor: Amir Mortazawi

Open to: Limited