CSE
CSE
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Defense Event

UNIFICATION OF VLSI PLACEMENT AND FLOORPLANNING

Saurabh Adya


 
Monday, May 17, 2004
2:00pm - 4:00pm
1005 EECS

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About the Event

“UNIFICATION OF VLSI PLACEMENT AND FLOORPLANNING” As VLSI circuits become larger and more complex, the need to improve design automation tools becomes more urgent. The interconnect effects dominate performance and power in the Deep Submicron (DSM) regime, and Computer Aided Design (CAD) tools and methodologies need to focus more on interconnect optimization. Additionally, there is a push for dramatic levels of on-chip integration in modern circuits. The cumulative effects of the two make design of leading-edge electronic products difficult. In this dissertation, we propose improved techniques and methodologies for layout design of modern VLSI chips. These techniques can be classified as floorplanning, mixed-size placement and placement for physical synthesis. The proposed algorithms address novel problem formulations and design concerns that arise in DSM VLSI designs.

Additional Information

Contact: Bert Wachsman

Phone: 763-4921

Email: bertw@eecs.umich.edu

Sponsor(s): ACAL

Open to: Public