Defense Event

Techniques for Frequency Synthesizer-­‐Based Transmitters

Mohammad Mahdi Ghahramani

PhD Candidate
Monday, April 13, 2015
2:00pm - 4:00pm
1340 EECS/LNF Conference Room

Add to Google Calendar

About the Event

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT system is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes in IoT standards makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and a simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters. The main contributions of this thesis are three fold. We introduce a novel frequency quadrupler with sub-picosecond jitter. The 192MHz quadrupler is ideal as a fast, low jitter reference for a low phase noise PLL and requires far less power and area than existing methods. The CMOS current reuse VCO is modified to reduce the supply voltage and achieve good phase noise with very low power consumption. A 2.5GHz prototype achieves the best figure of merit for any current reuse VCO. A fully integrated 2.4GHz transmitter for ZigBee based on a digital fractional-N PLL is presented. The prototype achieves an MSK modulation rate of 2Mb/s, delivers -2dBm of output power, and is free of in-band fractional spurs.

Additional Information

Sponsor(s): ECE

Faculty Sponsor: Michael P. Flynn

Open to: Public