Defense Event

Algorithm and architecture co-design for high performance digital signal processing

Jung Kuk Kim

PhD Candidate
Monday, April 27, 2015
10:00am - 12:00pm
1005 EECS

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About the Event

CMOS scaling has been the driving force behind the revolution of digital signal processing (DSP) systems, but scaling is slowing down and CMOS device is approaching to its fundamental scaling limit. At the same time, advanced DSP algorithms are continuing to evolve, so there is a growing gap between the increasing complexities of the algorithms and what is practically implementable. The growing gap can be bridged by exploring the synergy between algorithm design and hardware design, using the so-called co-design techniques. In this dissertation, the co-design techniques are applied to: 1) bio-inspired spiking neural networks (NNs) and 2) X-ray computed tomography (CT) image reconstruction. Co-designing starts from analysis of the algorithm characteristics such as sparse and random neuron spiking in NNs and high spatial and temporal locality in memory of CT. We then present how to leverage those interesting algorithm characteristics to implement high-performance and energy-efficient hardware. The throughput and energy efficiency of hardware are further improved using a number of algorithm and architecture techniques including damping neuron dynamics, pruning neuron-to-neuron connections, building a hierarchical architecture, sub-dividing building blocks, pipelining, and out-of-order scheduling. In particular, three hardware accelerators will be presented through the co-design techniques: 1) a 65nm CMOS sparse coding processor, 2) a 65nm CMOS neuromorphic object recognition processor, and 3) an FPGA-based CT forward projection accelerator. The co-design techniques can be applied to the design of other advanced DSP algorithms for emerging applications.

Additional Information

Sponsor(s): ECE

Faculty Sponsor: Zhengya Zhang, Jeffrey Fessler

Open to: Public