ECE
ECE
ECE ECE


Defense Event

Near-Threshold Computing: Past, Present, and Future

Nathaniel Pinckney


PhD Candidate
 
Wednesday, July 29, 2015
2:00pm - 4:00pm
1005 EECS

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About the Event

Transistor threshold voltages have stagnated in recent years, deviating from constant-voltage scaling theory and directly limiting supply voltage scaling. To overcome the resulting energy and power dissipation barriers, energy efficiency can be improved through aggressive voltage scaling, and there has been increased interest in operating at near-threshold computing (NTC) supply voltages. In this region sizable energy gains are achieved with moderate performance loss, some of which can be regained through parallelism. This talk delves into near-threshold computing in three parts. First, by providing a methodical definition of how near to threshold is “near threshold” and continuing with an in-depth examination of NTC across past CMOS process technologies. By systematically defining near-threshold, the trends and tradeoffs between different technologies are closely analyzed, lending insight in how best to design and optimize near-threshold systems. Second, we will look at a technique for fast voltage boosting, called Shortstop, in which a core's operating voltage is raised in 10s of cycles. Shortstop can be used to quickly respond to single-threaded performance demands of a near-threshold system by leveraging the innate parasitic inductance of a dedicated dirty supply rail, further improving energy efficiency. The technique is demonstrated in a wirebond implementation and is able to boost a core up to 1.8× faster than a header-based approach, while reducing supply droop by 2-7×. An improved flip-chip architecture is also proposed. Finally, the future of NTC in FinFET technologies is explored and compared with traditional planar processes. FinFET differs significantly from planar technology, with much better channel characteristics, which have the potential to dramatically improve near-threshold performance. Initial results show greater than 8× energy efficiency improvements when operating at NTC, reversing trends seen in planar technologies. Improved FinFET voltage scalability even enables energy gains when maximizing performance of a single task.

Additional Information

Sponsor(s): ECE

Faculty Sponsor: David Blaauw

Open to: Public