A Safety-First Approach to Memory Models
Wednesday, November 04, 2015|
2:00pm - 4:00pm
3725 Beyster Bldg.
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About the Event
Sequential consistency (SC) is arguably the most intuitive behavior for a shared-memory multithreaded program. It is widely accepted that language-level SC could significantly improve programmability of a multiprocessor system. However, efficiently supporting end-to-end SC remains a challenge as it requires that both compiler and hardware optimizations preserve SC semantics. Current concurrent languages support a relaxed memory model that requires programmers to explicitly annotate all memory accesses that can participate in a data race (``unsafe'' accesses). This requirement allows compiler and hardware to aggressively optimize unannotated accesses, which are assumed to be data-race-free (``safe'' accesses), while still preserving SC semantics. However, unannotated data races are easy for programmers to introduce accidentally and are difficult to detect, and in such cases the safety and correctness of programs are significantly compromised. In this thesis, we argue instead for a safety-first approach, whereby every memory operation is treated as potentially unsafe by the compiler and hardware unless it is proven otherwise. We propose DRFx memory model that provides SC for all programs by using a runtime memory model exception. We also propose compiler and hardware solutions to preserve SC at source-level. In addition to traditional multi-cores, we also study the cost of supporting SC in data-parallel architectures such as GPUs.
Sponsor(s): Satish Narayanasamy
Open to: Public