ECE
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Defense Event

Vertical Integration of Germanium Nanowires on Silicon Substrates for Nanoelectronics

Lin Chen


 
Monday, January 18, 2016
10:30am - 12:30pm
3316 EECS

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About the Event

Rapid development of semiconductor industry in recent years has been primarily driven by continuous scaling, which allows for manufacturing integrated circuits with higher computing power at a reduced cost. As the size of the transistors approaches tens of nanometers, we are now faced with new technological challenges brought by aggressive scaling. To this end, unconventional semiconductor material and novel device structure have attracted a lot of interests as promising candidates to replace MOSFET with Si channel and help extend the Moore’s law. In this dissertation, we focus on Vapor-Liquid-Solid (VLS) synthesized Germanium nanowires with nanoscale size, and investigate their potential as electronic devices. We discuss a strategy to grow vertical, taper-free Ge nanowires on Si with good flexibility and controllability. Specifically, we verify the presence of high-quality, abrupt Ge/Si heterojunction as a result of vertical integration. In addition, several single-nanowire vertical devices based on this material system are demonstrated, including heterodiode, junctionless transistor and tunnel transistor. Experimental characterization of these devices are complemented by various device models and good agreement is reached. 

Additional Information

Sponsor(s): ECE

Faculty Sponsor: Wei Lu

Open to: Public